View LTC17601_4299910.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

LTC1760 Dual Smart Battery System Manager DESCRIPTIO
The LTC(R)1760 Smart Battery System Manager is a highly integrated level 3 battery charger and selector intended for products using dual smart batteries. Three SMBus interfaces allow the LTC1760 to servo to the internal voltage and currents measured by the batteries while allowing an SMBus Host to monitor either battery's status. Charging accuracy is determined by the battery's internal voltage and current measurement, typically better than 0.2%. A proprietary PowerPathTM architecture supports simultaneous charging or discharging of both batteries. Typical battery run times are extended by up to 10%, while charging times are reduced by up to 50%. The LTC1760 automatically switches between power sources in less than 10s to prevent power interruption upon battery or wall adapter removal. The LTC1760 implements all elements of a version 1.1 "Smart Battery System Manager" except for the generation of composite battery information. An internal multiplexer cleanly switches the SMBus Host to either of the two attached Smart Batteries without generating partial messages to batteries or SMBus Host. Thermistors on both batteries are automatically monitored for temperature and disconnection information (SafetySignal).
, LTC and LT are registered trademarks of Linear Technology Corporation. PowerPath is a trademark of Linear Technology Corporation. Protected by U.S. Patents, including *5723970 **6650174
FEATURES

SMBus Charger/Selector for Two Smart Batteries* Voltage and Current Accuracy within 0.2% of Value Reported by Battery Simplifies Construction of "Smart Battery System Manager" Includes All SMBus Charger V1.1 Safety Features Supports Autonomous Operation without a Host Allows Both Batteries to Discharge Simultaneously into Single Load with Low Loss (Ideal Diode) SMBus Switching for Dual Batteries with Alarm Monitoring for Charging Battery at All Times Pin Programmable Limits for Maximum Charge Current and Voltage Improve Safety Fast Autonomous Power Path Switching (<10s) Low Loss Simultaneous Charging of Two Batteries >95% Efficient Synchronous Buck Charger AC Adapter Current Limiting* Maximizes Charge Rate SMBus Accelerator Improves SMBus Timing** Available in 48-Lead TSSOP Package
APPLICATIO S

Portable Computers and Instruments Standalone Dual Smart Battery Chargers Battery Backup Systems
TYPICAL APPLICATIO
DC IN
Dual Battery Charger/Selector System Architecture Dual vs Sequential Charging
SYSTEM POWER
LTC1760 SMBus (HOST)
SafetySignal 1 SMBus 1
3500 3000 2500 2000 1500 1000 500 0 3500 3000 2500 2000 1500 1000 500 0 0
BATTERY CURRENT (mA)
BAT1 CURRENT
SafetySignal 2 SMBus 2
1760 TA01
BATTERY TYPE: 10.8V Li-Ion (MOLTECH NI2020) REQUESTED CURRENT = 3A REQUESTED VOLTAGE = 12.3V MAX CHARGER CURRENT = 4.1A 1760 TA03
U
U
U
BAT1 CURRENT
BAT2 CURRENT SEQUENTIAL
BAT2 CURRENT
DUAL 100 MINUTES
50
100 150 200 TIME (MINUTES)
250
300
1760f
1
LTC1760
ABSOLUTE
(Note 1)
AXI U RATI GS
PACKAGE/ORDER I FOR ATIO
TOP VIEW VPLUS BAT2 BAT1 SCN SCP GDCO GDCI GB1O GB1I GB2O GB2I LOPWR VSET ITH ISET DCDIV SCL2 SCL SCL1 VDDS SDA2 SDA SDA1 GND 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 FW PACKAGE 48-LEAD PLASTIC TSSOP 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 SCH2 GCH2 GCH1 SCH1 TGATE BOOST SW DCIN VCC BGATE PGND COMP1 CLP CSP CSN VLIMIT ILIMIT TH1B TH1A SMBALERT TH2A TH2B MODE VCC2
Voltage from DCIN, SCP, SCN, CLP, VPLUS, SW to GND ................................... 32V/-0.3 V Voltage from SCH1, SCH2 to GND ................ 28V/-0.3 V Voltage from BOOST to GND ........................ 37V/ -0.3V CSP, CSN, BAT1, BAT2 to GND ..................... 28V/-0.3V LOPWR, DCDIV to GND ................................ 10V/ -0.3V Voltage from VCC2, VDDS to GND .................... 7V/-0.3 V SDA1, SDA2, SDA, SCL1, SCL2, SCL, SMBALERT to GND ........................................................ 7V/-0.3V MODE to GND ..................................... VCC2 +0.3V/-0.3V COMP1 to GND ............................................... 5V/ -0.3V Maximum DC Current Into Pin SDA1, SDA2, SDA, SCL1, SCL2, SCL .............. 3mA TH1A, TH2A ..................................................... -5mA TH1B, TH2B .................................................. -102A Operating Ambient Temperature (Note 6) .... 0C to 70C Operating Junction Temperature ...........-40C to 125C Storage Temperature .............................-65C to 150C Lead Temperature (Soldering, 10 sec).................. 300C
ORDER PART NUMBER LTC1760CFW
TJMAX = 125C, JA = 110C/W
Consult LTC Marketing for parts specified with wider operating temperature ranges.
The denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25C. VDCIN = 20V, VBAT1 = 12V, VBAT2 = 12V, VVDDS = 3.3V, VVCC2 = 5.2V unless otherwise noted.
SYMBOL PARAMETER DCIN Operating Range ICH0 ICH1 IVCC2_AC1 IVCC2_AC0 DCIN Operating Current VCC2 Operating Current CONDITIONS DCIN Selected Not Charging (DCIN Selected) (Note 10) Charging (DCIN Selected) (Note 10) AC Present (Note 11) AC Not Present (Note 11) 6 0 175 0.8 0.7 0.7 0.7 IVCC = 0mA to 10mA With Respect to Voltage Reported by Battery VCHMIN < Requested Voltage < VLIMIT -32 3 4.9 5.2 0.2 5 5.5 1 32 MIN 6 1 1.3 0.75 75 TYP MAX 28 1.5 2 1 100 28 28 UNITS V mA mA mA A V V A V V V V V V % mV
1760f
ELECTRICAL CHARACTERISTICS
Supply and Reference
Battery Operating Voltage Range Battery Selected, PowerPath Function Battery Selected, Charging Function (Note 2) IBAT VFDC VFB1 VFB2 VFSCN UVLO VVCC VLDR VTOL Battery Drain Current VPLUS Diodes Forward Voltage: DCIN to VPLUS BAT1 to VPLUS BAT2 to VPLUS SCN to VPLUS VCC Regulator Output Voltage VCC Load Regulation Voltage Accuracy Battery Selected, Not Charging, VDCIN = 0V (Note 10) IVCC = 10mA IVCC = 0mA IVCC = 0mA IVCC = 0mA
Undervoltage Lockout Threshold VPLUS Ramping Down, Measured at VPLUS to GND
Switching Regulator
2
U
W
U
U
WW
W
LTC1760
The denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25C. VDCIN = 20V, VBAT1 = 12V, VBAT2 = 12V, VVDDS = 3.3V, VVCC2 = 5.2V unless otherwise noted.
SYMBOL ITOL PARAMETER Current Accuracy CONDITIONS With Respect to Current Reported by Battery 4mV/RSENSE < Requested Current < ILIMIT (Min) (Note 12) RILIMIT = 0 (Short to GND) RILIMIT = 10k 1% RILIMIT = 33k 1% RILIMIT = Open (or Short ILIMIT to VCC2) Duty Cycle 99% MIN TYP MAX UNITS
ELECTRICAL CHARACTERISTICS

-2 -4 -8 -8 255 20 99 300 25 99.5 155 150 0
2 4 8 8 345
mA mA mA mA kHz kHz %
f0SC fDO DCMAX IMAX ISNS CMSL CMSH VCL1
Regulator Switching Frequency Regulator Switching Frequency in Low Dropout Mode Regulator Maximum Duty Cycle Maximum Current Sense Threshold CA1 Input Bias Current CA1/I1 Input Common Mode Low CA1/I1 Input Common Mode High CL1 Turn-On Threshold
VITH = 2.2V VCSP = VCSN > 5V
140
190
mV A V
VDCIN - 0.2 95 94 100 100 50 50 50 40
V mV mV ns ns ns ns V mV nA mV V %
105 108 90 90 90 80 1.215 200 115 7.9
TG tr TG tf BG tr BG tf Trip Points VTR VTHYS IBVT VTSC VFTO VOVSD DACs IRES tIP tILOW
TGATE Transition Time: TGATE Rise Time TGATE Fall Time BGATE Transition Time: BGATE Rise Time BGATE Fall Time DCDIV/LOPWR Threshold DCDIV/LOPWR Hysteresis Voltage DCDIV/LOPWR Input Bias Current Short-Circuit Comparator Threshold Fast Power Path Turn-Off Threshold Overvoltage Shutdown Threshold as a Percent of Programmed Charger Voltage IDAC Resolution IDAC Pulse Period: Normal Mode Wake-Up Mode Charging Current Granularity
CLOAD = 3300pF, 10% to 90% CLOAD = 3300pF, 10% to 90% CLOAD = 3300pF, 10% to 90% CLOAD = 3300pF, 10% to 90% VDCDIV or VLOPWR Falling VDCDIV or VLOPWR Rising VDCDIV or VLOPWR = 1.19V VSCP - VSCN, VCC 5V VDCDIV Rising from VCC VSET Rising from 0.8V until TGATE and BGATE Stop Switching Guaranteed Monotonic 10 6 RILIMIT = (Short ILIMIT to GND) RILIMIT = 10k 1% RILIMIT = 33k 1% RILIMIT = Open (or Short ILIMIT to VCC2 ) 60 RILIMIT = 0 (Short ILIMIT to GND) RILIMIT = 10k 1% RILIMIT = 33k 1% RILIMIT = Open (or Short ILIMIT to VCC2 ) Guaranteed Monotonic (5V < VBAT < 25V)

1.166
1.19 30 20
90 6
100 7 107
Bits 10 50 1 2 4 4 80 1000 2000 3000 4000 100 1070 2140 3210 4280 15 s ms mA mA mA mA mA mA mA mA mA Bits
1760f
IWAKE_UP ILIMIT
Wake-Up Charging Current (Note 5) Charging Current Limit
980 1960 2490 3920 11
VRES
VDAC Resolution
3
LTC1760
ELECTRICAL CHARACTERISTICS
SYMBOL VSTEP VLIMIT PARAMETER VDAC Granularity Charging Voltage Limit (Note 7)
The denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25C. VDCIN = 20V, VBAT1 = 12V, VBAT2 = 12V, VVDDS = 3.3V, VVCC2 = 5.2V unless otherwise noted.
CONDITIONS RVLIMIT = 0 (Short VLIMIT to GND) RVLIMIT = 10k 1% RVLIMIT = 33k 1% RVLIMIT = 100k 1% RVLIMIT = Open (or Short VLIMIT to VCC2 )(Note 13) VGCHX - VSCHX > 3V, CLOAD = 3000pF VGCHX - VSCHX < 1V, from Time of VCSN < VBATX - 30mV, CLOAD = 3000pF ILOAD = 1A VGCH1 - VSCH1 VGCH2 - VSCH2 ILOAD =10A VGCH1 - VSCH1 VGCH2 - VSCH2 VBATX - VCSN, 5V VBATX 28V VCSN - VBATX, 5V VBATX 28V VGCHX - VSCHX = 1.5V -2 2 3.5 4.7 A A V

MIN 8400 12608 16832 21024
TYP 16 8432 12640 16864 21056 32768 5 15
MAX 8464 12672 16896 21088
UNITS mV mV mV mV mV mV ms s
Charge Mux Switches tONC tOFFC VCON GCH1/GCH2 Turn-On Time GCH1/GCH2 Turn-Off Time CH Gate Clamp Voltage GCH1 GCH2 CH Gate Off Voltage GCH1 GCH2 CH Switch Reverse Turn-Off Voltage CH Switch Forward Regulation Voltage GCH1/GCH2 Active Regulation: Max Source Current Max Sink Current BATX Voltage Below Which Charging is Inhibited (Does Not Apply to Wake-Up Mode) Blanking Period after UVLO Trip Blanking Period after LOPWR Trip GB1O/GB2O/GDCO Turn-On Time GB1O/GB2O/GDCO Turn-Off Time Output Gate Clamp Voltage GB1O GB2O GDCO Output Gate Off Voltage GB1O GB2O GDCO PowerPath Switch Reverse Turn-Off Voltage PowerPath Switch Forward Regulation Voltage GDCI/GB1I/GB2I Active Regulation: Source Current Sink Current Switches Held Off Switches in 3-Diode Mode VGS < -3V, from Time of Battery/DC Removal, or LOPWR Indication, CLOAD = 3000pF VGS > -1V, from Time of Battery/DC Removal, or LOPWR Indication, CLOAD = 3000pF ILOAD = 1A Highest (VBAT1 or VSCP) - VGB1O Highest (VBAT2 or VSCP) - VGB2O Highest (VDCIN or VSCP) - VGDCO ILOAD = -25A Highest (VBAT1 or VSCP) - VGB1O Highest (VBAT2 or VSCP) - VGB2O Highest (VDCIN or VSCP) - VGDCO VSCP - VBATX or VSCP - VDCIN 6V VSCP 28V VBATX - VSCP or VDCIN - VSCP 6V VSCP 28V (Note 3) -4 75 A A
1760f
10
5 5 -0.8 -0.8 5 15
5.8 5.8 -0.4 -0.4 20 35
7 7 0 0 40 60
V V V V mV mV
VCOFF
VTOC VFC IOC(SRC) IOC(SNK) VCHMIN
PowerPath Switches tDLY tPPB tONPO tOFFPO VPONO 250 1

ms sec 10 7 s s
5 3
4.75 4.75 4.75
6.25 6.25 6.25 0.18 0.18 0.18
7 7 7 0.25 0.25 0.25 60 50
V V V V V V mV mV
VPOFFO
VTOP VFP

5 0
20 25
IOP(SRC) IOP(SNK)
4
LTC1760
The denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25C. VDCIN = 20V, VBAT1 = 12V, VBAT2 = 12V, VVDDS = 3.3V, VVCC2 = 5.2V unless otherwise noted.
SYMBOL tONPI tOFFPI VPONI PARAMETER Gate B1I/B2I/DCI Turn-On Time Gate B1I/B2I/DCI Turn-Off Time Input Gate Clamp Voltage GB1I GB2I GDCI Input Gate Off Voltage GB1I GB2I GDCI Thermistor Trip (COLD-RANGE/OVER-RANGE) Thermistor Trip (IDEAL-RANGE/COLD-RANGE) Thermistor Trip (HOT-RANGE/IDEAL-RANGE) Thermistor Trip (UNDER-RANGE/HOT-RANGE) Logic Levels SCL/SCL1/SCL2/SDA/SDA1/ SDA2 Input Low Voltage (VIL) SCL/SCL1/SCL2/SDA/SDA1/ SDA2 Input High Voltage (VIH) SCL/SCL1/SCL2/SDA/SDA1/ SDA2 Input Leakage Current SCL/SCL1/SCL2/SDA/SDA1/ SDA2 Input Leakage Current IPULLUP SCL1/SDA1/SCL2/SDA2 Pull-Up Current When Not Connected to SMBus Host SCL1/SDA1/SCL2/SDA2 Series Impedance to Host SMBus SCL/SDA Output Low Voltage (VOL). LTC1760 Driving the Pin SCL1/SDA1/SCL2/SDA2 Pullup Output Low Voltage (VOL). LTC1760 Driving the Pin with Battery SMBus not Connected to Host SMBus SCL1/SDA1/SCL2/SDA2 Output Low Voltage (VOL). LTC1760 Driving the Pin with Battery SMBus Connected to Host SMBus VSDA, VSCL, VSDA1, VSCL1, VSDA2, VSCL2 = 0.8V VSDA, VSCL, VSDA1, VSCL1, VSDA2, VSCL2 = 2.1V VSCL1 = VSDA1 = VSCL2 = VSDA2 = 0.4V VVCC2 = 4.85V and 5.55V (Current is Through Internal Series Resistor and Schottky to VCC2) VSDA1, VSCL1, VSDA2, VSCL2 = 0.8V IPULLUP = 350A IPULLUP Internal to LTC1760

ELECTRICAL CHARACTERISTICS
CONDITIONS VGS < -3V, CLOAD = 3000pF (Note 4) VGS > -1V, CLOAD = 3000pF (Note 4) ILOAD = 1A Highest (VBAT1 or VSCP) - VGB1I Highest (VBAT2 or VSCP) - VGB2I Highest (VDCIN or VSCP) - VGDCI ILOAD = -25A Highest (VBAT1 or VSCP) - VGB1I Highest (VBAT2 or VSCP) - VGB2I Highest (VDCIN or VSCP) - VGDCI CLOAD(MAX) = 300pF (Note 9) R1A = R2A = 1130 1% R1B = R2B = 54900 1% CLOAD(MAX) = 300pF (Note 9) R1A = R2A = 1130 1% R1B = R2B = 54900 1% CLOAD(MAX) = 300pF (Note 9) R1A = R2A = 1130 1% R1B = R2B = 54900 1% CLOAD(MAX) = 300pF (Note 9) R1A = R2A = 1130 1% R1B = R2B = 54900 1%
MIN
TYP 300 10
MAX
UNITS s s
4.75 4.75 4.75
6.7 6.7 6.7 0.18 0.18 0.18
7.5 7.5 7.5 0.25 0.25 0.25 105
V V V V V V k
VPOFFI
Thermistor 95 100
28.5
30
32.5
k
2.85
3
3.15
k
425
500
575
0.8 2.1 -5 -5 165 220 5 5 350
V V A A A
300 0.4 0.4
V V
IPULLUP = 350A on Host Side
0.4
V
1760f
5
LTC1760
The denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25C. VDCIN = 20V, VBAT1 = 12V, VBAT2 = 12V, VVDDS = 3.3V, VVCC2 = 5.2V unless otherwise noted.
SYMBOL PARAMETER SCL/SCL1/SCL2/SDA/SDA1/ SDA2/ SMBALERT Power Down Leakage SMBALERT Output Low Voltage (VOL) SMBALERT Output Pull-Up Current VIL_VDDS VIH_VDDS VDDS Input Low Voltage (VIL) VDDS Input High Voltage (VIH) VDDS Operating Voltage VDDS Operating Current MODE Input Low Voltage (VIL) MODE Input High Voltage (VIH) MODE Input Current (IIH) MODE Input Current (IIL) Charger Timing tTIMEOUT tQUERY SMBus Timing SCL Serial-Clock High Period(tHIGH) SCL Serial-Clock Low Period (tLOW) SDA/SCL Rise Time (tr) SDA/SCL Fall Time (tf) SMBus Accelerator Trip Voltage Range Start-Condition Setup Time (tSU:STA) Start-Condition Hold Time (tHD:STA) SDA to SCL Rising-Edge Setup Time (tSU:DAT) SDA to SCL Falling-Edge Hold Time, Slave Clocking in Data (tHD:DAT) tTIMEOUT_SMB The LTC1760 will Release the SMBus and Terminate the Current Master or Slave Command if the Command is not Completed Before this Time Note 1: Absolute Maximum Ratings are those values beyond which the life of a device may be impaired. Note 2. Battery voltage must be adequate to drive gates of power path P-channel FET switches. This does not affect charging voltage of the battery, which can be zero volts during wake-up charging. Note 3. DCIN, BAT1, BAT2 are held at 12V and GDCI, GB1I, GB2I are forced to 10.5V. SCP is set at 12V to measure source current at GDCI, GB1I and GB2I. SCP is set at 11.9V to measure sink current at GDCI, GB1I and GB2I. Note 4. Extrapolated from testing with CL = 50pF. Note 5. Accuracy dependent upon external sense resistor and compensation components. At IPULLUP = 350A, CLOAD = 150pF (Note 8) At IPULLUP = 350A, CLOAD = 150pF (Note 8) CLOAD = 150pF, RPU = 9.31k (Note 8) CLOAD = 150pF, RPU = 9.31k (Note 8)

ELECTRICAL CHARACTERISTICS
CONDITIONS VVCC2 = 0V, VVDDS = 0V, VSCL, VSCL1, VSCL2, VSDA, VSDA1, VSDA2, VSMBALERT = 5.5V IPULLUP = 500A VSMBALERT = 0.4V

MIN
TYP
MAX 2
UNITS uA
0.4 3.5 2.6 3 10 17.5 1.5 5.5 18 VVCC2 * 0.3 VVCC2 * 0.7 -1 -1 140 175 1 1 1 210
V A V V V A V V A A sec sec
VSCL, VSDA = VVDDS , VVDDS = 5V VVCC2 = 4.85V VVCC2 = 4.85V MODE = VVCC2 * 0.7V, VVCC2 = 4.85V MODE = VVCC2 * 0.3V, VVCC2 = 4.85V

VIL_MODE VIH_MODE
Timeout for Wake-Up Charging and Controlled Charging Sampling Rate Used by the LTC1760 to Update Charging Parameters
4 4.7 1000 300 0.8 4.7 4 250 300 25 35 1.42
s s ns ns V s s ns ns ms
Note 6. The LTC1760C is guaranteed to meet specified performance from 0C to 70C and is designed, characterized and expected to meet specified performance at -40C and 85C, but is not tested at these extended temperature limits. Note 7. Charger servos to the value reported by a Voltage() query. This is the internal cell voltage measured by the battery electronics and may be lower than the terminal voltage. See "Operation Section 3.6" for more information. Note 8. CLOAD is the combined capacitance on the host's SMBus connection and the selected battery's SMBus connection. Note 9. CLOAD_MAX is the maximum allowed combined capacitance on THxA, THxB and the battery's SafetySignalx connections.
1760f
6
LTC1760
ELECTRICAL CHARACTERISTICS
Note 10. Does not include current supplied by VCC to VCC2 (IVCC2_AC1 or IVCC2_AC0) Note 11. Measured with thermistors not present, RVILIM and RILIM removed and SMBALERT = 1. See Applications Information section: "Calculating IC Operating Current" for example on how to calculate total IC operating current. Note 12. Requested currents below 44mV/RSENSE may not servo correctly due to charger offsets. The charging current for requested currents below 4mV/RSENSE will be between 4mV/RSENSE and (Requested Current - 8mA). Refer to Applications Information: "Setting Charger Output Current Limit" for values of RSENSE. Note 13. This limit is greater than the absolute maximum for the charger. Therefore, there is no effective limitation for the voltage when this option is selected.
TYPICAL PERFOR A CE CHARACTERISTICS
Charging Voltage Accuracy
0 Current()-ChargingCurrent() (mA)
Voltage()-ChargingVoltage() (mV)
0 -5 -10 -15 -20
-10
BATTERY CURRENT (mA)
-5
-15
-20
-25 4700
7132 11996 14428 9564 ChargingVoltage() (mV)
Dual Charging Batteries with Different Charge State
17.0 16.5 BAT2 VOLTAGE BAT1 VOLTAGE 3500
12.0
BATTERY VOLTAGE (V)
BATTERY VOLTAGE (V)
16.0 15.5 15.0 14.5 14.0 13.5 0 BAT2 CURRENT 20
2500 2000 1500 BAT1 CURRENT 1000 500
BATTERY VOLTAGE (V)
0 40 60 80 100 120 140 160 TIME (MINUTES)
BAT1 INITIAL CAPACITY = 0% BAT2 INITIAL CAPACITY = 90% PROGRAMMED CHARGER CURRENT = 3A PROGRAMMED CHARGER VOLTAGE = 16.8V
UW
1760 G01
Charging Current Accuracy
10 5
3500 3000 2500 2000 1500 1000 500 0 3500 3000 2500 2000 1500 1000 500 0
Dual Battery Charge Time vs Sequential Battery Charging
BAT1 CURRENT BAT2 CURRENT SEQUENTIAL
BAT1 CURRENT
BAT2 CURRENT
DUAL 100 MINUTES
16860
0
800
1600 2400 3200 ChargingCurrent() (mA)
4000
1760 G02
0
50
100 150 200 TIME (MINUTES)
250
300
BATTERY TYPE: 10.8V Li-Ion (MOLTECH NI2020) REQUESTED CURRENT = 3A REQUESTED VOLTAGE = 12.3V MAX CHARGER CURRENT = 4.1A 1760 G03
Dual Battery Discharge Time vs Sequential Battery Discharge (Li-Ion)
15 11.0 BAT1 VOLTAGE BAT2 VOLTAGE BAT2 VOLTAGE DUAL 14 13 12 11 10 15 14 13 12 11 MINUTES 11 10
Dual Battery Dischage Time vs Sequential Battery Discharge (NiMH)
BAT2 VOLTAGE BAT1 VOLTAGE BAT2 VOLTAGE BAT1 VOLTAGE 16 MINUTES 0 20 40 60 80 100 TIME (MINUTES) 120 140
3000
DUAL
1760 G04
BATTERY CURRENT (mA)
10.0 9.0 8.0 12.0 11.0 10.0 9.0 8.0 0 20 40
SEQUENTIAL
SEQUENTIAL
BAT1 VOLTAGE
60 80 100 120 140 160 180 TIME (MINUTES)
BATTERY TYPE: 10.8V Li-Ion (MOLTECH NI2020) LOAD CURRENT = 3A 1760 G05
BATTERY TYPE: 12V NiMH (MOLTECH NJ1020) 1760 G06 LOAD: 33W
1760f
7
LTC1760 TYPICAL PERFOR A CE CHARACTERISTICS
Efficiency vs Charging Current
100 90 80
BAT1 VOLTAGE (V)
BAT1 VOLTAGE (V)
EFFICIENCY (%)
70 60 50 40 30 20 10 0 0 0.025 0.50 0.10 IOUT (A) 2.5 4.0
1760 G07
Power Path Switching 1 and 2
16 15 14 CLOAD = 20F ILOAD = 0.8A TA = 25C
5V
LOAD VOLTAGE (V)
13 12 11 10 9 8 7 6 -50 -40 -30 -20 -10 0 10 20 30 40 50 TIME (s)
1960 G10
PI FU CTIO S
Input Power Related
SCN (Pin 4): PowerPath Current Sensing Negative Input. This pin should be connected directly to the "bottom" (output side) of the low valued resistor in series with the three PowerPath switch pairs, for detecting short-circuit current events. Also powers the LTC1760 internal circuitry when all other sources are absent. SCP (Pin 5): PowerPath Current Sensing Positive Input. This pin should be connected directly to the "top" (switch side) of the low valued resistor in series with the three PowerPath switch pairs, for detecting short-circuit current events. GDCO (Pin 6): DCIN Output Switch Gate Drive. Together with GDCI, this pin drives the gate of the P-channel switch in series with the DCIN input switch. GDCI (Pin 7): DCIN Input Switch Gate Drive. Together with GDCO, this pin drives the gate of the P-channel switch connected to the DCIN input. GB1O (Pin 8): BAT1 Output Switch Gate Drive. Together with GB1I, this pin drives the gate of the P-channel switch in series with the BAT1 input switch. GB1I (Pin 9): BAT1 Input Switch Gate Drive. Together with GB1O, this pin drives the gate of the P-channel switch connected to the BAT1 input.
1760f
8
UW
Load Dump
14 12 10 8 6 4 2 0 -4 -2 BAT1 OUTPUT VIN = 20V VDAC = 12.29V IDAC = 3000mA LOAD CURRENT = 1A TA = 25C LOAD CONNECTED LOAD DISCONNECTED 0 2 468 TIME (ms) 10 12 14 16
1760 G08
Load Regulation
12.4 12.3 12.2 12.1 12.0 11.9 11.8 11.7 11.6 0 VIN = 20V VDAC = 12.288V IDAC = 4000mA TA = 25C 1000 2000 3000 CHARGE CURRENT (mA) 4000
1760 G09
SMBus Accelerator Operation
VCC = 5V CLD = 200pF TA = 25C
LTC1760
RPULLUP = 15k
LOPWR THRESHOLD
0V
1s/DIV
1760 G11
U
U
U
LTC1760
PI FU CTIO S
GB2O (Pin 10): BAT2 Output Switch Gate Drive. Together with GB2I, this pin drives the gate of the P-channel switch in series with the BAT2 input switch. GB2I (Pin 11): BAT2 Input Switch Gate Drive. Together with GB2O, this pin drives the gate of the P-channel switch connected to the BAT2 input. CLP (Pin 36): This is the Positive Input to the Supply Current Limiting Amplifier CL1. The threshold is set at 100mV above the voltage at the DCIN pin. When used to limit supply current, a filter is needed to filter out the switching noise. COMP1 (Pin 37): This is the Compensation Node for the Amplifier CL1. A capacitor is required from this pin to GND if input current amplifier CL1 is used. At input adapter current limit, this node rises to 1V. By forcing COMP1 to GND, amplifier CL1 will be defeated (no adapter current limit). COMP1 can source 10A. BGATE (Pin 39): Drives the Gate of the Bottom External MOSFET of the Battery Charger Buck Converter. SW (Pin 42): Connected to Source of Top External MOSFET Switch. Used as reference for top gate driver. BOOST (Pin 43): Supply to Topside Floating Driver. The bootstrap capacitor is returned to this pin. Voltage swing at this pin is from a diode drop below VCC to (DCIN + VCC). TGATE (Pin 44): Drives the Gate of the Top External MOSFET of the Battery Charger Buck Converter. SCH1 (Pin 45), SCH2 (Pin 48): Charger MUX Switch Source Returns. These two pins are connected to the sources of Q3/Q4 and Q9/Q10 (see Typical Applications). A small pull-down current source returns these nodes to 0V when the switches are turned off. GCH1 (Pin 46), GCH2 (Pin 47): Charger MUX Switch Gate Drives. These two pins drive the gates of the backto-back N-channel switch pairs, Q3/Q4 and Q9/Q10, between the charger output and the two batteries (see Typical Applications).
Battery Charging Related
VSET (Pin 13): The Tap Point of a Programmable Resistor Divider which Provides Battery Voltage Feedback to the Charger. A capacitor from CSN to VSET and one from VSET to GND provide necessary compensation and filtering for the voltage loop. ITH (Pin 14): This is the Control Signal of the Inner Loop of the Current Mode PWM. Higher ITH corresponds to higher charging current in normal operation. A capacitor of at least 0.1F to GND filters out PWM ripple. Typical fullscale output current is 30A. Nominal voltage range for this pin is 0V to 2.4V. ISET (Pin 15): A Capacitor from ISET to GND is Required to Filter Higher Frequency Components from the Delta-Sigma IDAC. ILIMIT (Pin 32): An external resistor (RILIMIT) is connected between this pin and GND. The value of the external resistor programs the range and resolution of the programmed charger current. VLIMIT (Pin 33): An external resistor (RVLIMIT)is connected between this pin and GND. The value of the external resistor programs the range and resolution of the voltage DAC. CSN (Pin 34): Current Amplifier CA1 Input. Connect this to the common output of the charger MUX switches. CSP (Pin 35): Current Amplifier CA1 Input. This pin and the CSN pin measure the voltage across the sense resistor, RSENSE, to provide the instantaneous current signals required for both peak and average current mode operation.
U
U
U
External Power Supply Pins
VPLUS (Pin 1): Supply. The VPLUS pin is connected via four internal diodes to the DCIN, SCN, BAT1, and BAT2 pins. Bypass this pin with a 0.1F capacitor and a 1F capacitor. See Typical Applications for complete circuit. BAT1 (Pin 3), BAT2 (Pin 2): These two pins are the inputs from the two batteries for power to the LTC1760. LOPWR (Pin 12): LOPWR Comparator Input from External Resistor Divider Connected from SCN to GND. If the voltage at LOPWR pin is lower than the LOPWR comparator threshold, then system power has failed and power is autonomously switched to a higher voltage source, if available.
1760f
9
LTC1760
PI FU CTIO S
DCDIV (Pin 16): DCDIV Comparator Input from External Resistor Divider Connected from DCIN to GND. If the voltage at DCDIV pin is above the DCDIV comparator threshold, then the AC_PRESENT bit is set and the wall adapter power is considered to be adequate to charge the batteries. If DCDIV is taken more than 1.8V above VCC, then all of the power path switches are latched off until all power is removed. DCIN (Pin 41): Supply. External DC power source. A 0.1F bypass capacitor must be connected to this pin as close as possible. No series resistance is allowed, since the adapter current limit comparator input is also this pin. SDA2 (Pin 21): SMBus Data Signal to Smart Battery 2. Do not connect to an external pull-up. The LTC1760 connects this pin to an internal pull-up (IPULLUP) when required. SDA (Pin 22): SMBus Data Signal to SMBus Host. Also used to indicate charging status of Battery 2. Requires an external pullup to VDDS. Connected to internal SMBus accelerator. SDA1 (Pin 23): SMBus Data Signal to Smart Battery 1. Do not connect to an external pull-up. The LTC1760 connects this pin to an internal pull-up (IPULLUP) when required. MODE (Pin 26): Used in conjunction with VDDS to allow SCL, SDA and SMBALERT to indicate charging status. May also be used as a hardware charge inhibit. TH2B (Pin 27): Thermistor Force/Sense Connection to Smart Battery 2 SafetySignal. Connect to Battery 2 thermistor through resistor network shown in "Typical Application." TH2A (Pin 28): Thermistor Force/Sense Connection to Smart Battery 2 SafetySignal. Connect to Battery 2 thermistor through resistor network shown in "Typical Application." SMBALERT (Pin 29): Active Low Interrupt Pin. Signals SMBus Host that there has been a change of status in battery or AC presence. Open drain with weak current source pull-up to VCC2 (with Schottky to allow it to be pulled to 5V externally). Also used to indicate charging status of Battery 1. TH1A (Pin 30): Thermistor Force/Sense Connection to Smart Battery 1 SafetySignal. Connect to Battery 1 thermistor through resistor network shown in "Typical Application." TH1B (Pin 31): Thermistor Force/Sense Connection to Smart Battery 1 SafetySignal. Connect to Battery 1 thermistor through resistor network shown in "Typical Application."
Internal Power Supply Pins
VDDS (Pin 20): Power Supply for SMBus Accelerators. Also used in conjunction with MODE pin to modify the LTC1760 operating mode. GND (Pin 24): Ground for Low Power Circuitry. VCC2 (Pin 25): The VCC2 Power Supply is used Primarily to Power Internal Logic Circuitry. Must be connected to VCC. PGND (Pin 38): High Current Ground Return for BGATE Driver. VCC (Pin 40): Internal Regulator Output. Bypass this output with at least a 2F to 4.7F capacitor. Do not use this regulator output to supply external circuitry except as shown in the application circuit.
SBS Interface Pins
SCL2 (Pin 17): SMBus Clock Signal to Smart Battery 2. Do not connect to an external pull-up. The LTC1760 connects this pin to an internal pull-up (IPULLUP) when required. SCL (Pin 18): SMBus Clock Signal to SMBus Host. Also used to determine flashing rate for stand-alone charge indicators. Requires an external pullup to VDDS (normal SMBus operating mode). Connected to internal SMBus accelerator. SCL1 (Pin 19): SMBus Clock Signal to Smart Battery 1. Do not connect to an external pull-up. The LTC1760 connects this pin to an internal pull-up (IPULLUP) when required.
10
U
U
U
1760f
LTC1760
BLOCK DIAGRA W
GB1I GB1O 9 8 GB2I GB2O 11 10 GDCI GDCO 7 6 100mV SWB1 DRIVER SWB2 DRIVER SWDC DRIVER SHORT CIRCUIT + LIMIT DECODER DCIN CHARGE PUMP VCC2 10A GCH1 46 SCH1 45
ON ON
5 SCP 100 4 SCN 32 ILIMIT 33 VLIMIT
SCH2 48 BAT1 BAT2 3 2 CHARGE VPLUS 1 SCN AC_PRESENT SMBus INTERFACE
VCC2 25 VCC 40 GND 24 VCC REGULATOR
1.19V DCIN 41
TGATE 44 SW 42 VCC BGATE 39 PGND 38 DCIN 100mV CLP 36 + CL1 - gm = 0.4m IREV PWM LOGIC Q R /15 S ICMP
BUFFERED ITH
3mV - -
gm = 1.4m
37 COMP1
14 ITH
+
EA
11-BIT VOLTAGE DAC
0.8V
1760 BD
+
BOOST 43
CA2
-
+
+
-
BGATE
TON
gm = 1.4m
+
LOW DROP DETECT
+
OSCILLATOR
CA1
-
CSN
0V
-
+
LOPWR 12
+
DCDIV 16
-
-
+ -
GCH2 47
SEQUENCER CSN
SAFETY SIGNAL DECODER
PowerPath CONTROLLER
10-BIT CURRENT DAC
0.86V
- CSP-CSN 3k 3k 3k 0.8V
+ -
29 SMBALERT
26 MODE 20 VDDS 18 SCL 22 SDA 19 SCL1 23 SDA1 17 SCL2 21 SDA2 30 TH1A 31 TH1B 28 TH2A 27 TH2B 15 ISET
35 CSP 34 CSN
-+
40mV 400k 13 VSET
1760f
11
LTC1760
TABLE OF CO TE TS
1 Overview .............................................................................................................................................................................................. 13 2 The SMBus Interface ........................................................................................................................................................................... 13 2.1 SMBus Interface Overview ............................................................................................................................................................... 13 2.2 Data Bit Definition of Supported SMBus Functions. ......................................................................................................................... 14 2.3 Description of Supported SMBus Functions .................................................................................................................................... 16 2.3.1 BatterySystemState() ('h01) ........................................................................................................................................................ 16 2.3.2 BatterySystemStateCont() ('h02) ................................................................................................................................................. 17 2.3.3 BatterySystemInfo() ('h04) .......................................................................................................................................................... 18 2.3.4 LTC() ('h3c) ................................................................................................................................................................................. 19 2.3.5 BatteryMode() ('h03) ................................................................................................................................................................... 19 2.3.6 Voltage() ('h09) ........................................................................................................................................................................... 19 2.3.7 Current() ('h0a) ............................................................................................................................................................................ 20 2.3.8 ChargingCurrent() ('h14) ............................................................................................................................................................. 20 2.3.9 ChargingVoltage() ('h15) ............................................................................................................................................................. 20 2.3.10 AlarmWarning() ('h16) ................................................................................................................................................................ 20 2.3.11 AlertResponse() ........................................................................................................................................................................... 21 2.4 SMBus Dual Port Operation ............................................................................................................................................................. 21 2.5 LTC1760 SMBus Controller Operation ............................................................................................................................................. 22 2.6 LTC1760 SMBALERT Operation ...................................................................................................................................................... 24 3 Charging Algorithm Overview .............................................................................................................................................................. 24 3.1 Wake-Up Charging Initiation ............................................................................................................................................................ 24 3.2 Wake-Up Charging Termination ....................................................................................................................................................... 24 3.3 Wake-Up Charging Current and Voltage Limits ............................................................................................................................... 25 3.4 Controlled Charging Initiation .......................................................................................................................................................... 25 3.5 Controlled Charging Termination ..................................................................................................................................................... 25 3.6 Controlled Charging Current and Voltage Programming .................................................................................................................. 26 4 System Power Management Algorithm and Battery Calibration .......................................................................................................... 27 4.1 Turning Off System Power ............................................................................................................................................................... 27 4.2 Power-By Algorithm When No Battery is Being Calibrated .............................................................................................................. 27 4.3 Power-By Algorithm When a Battery is Being Calibrated ................................................................................................................. 27 4.4 Power-By Reporting ........................................................................................................................................................................ 27 5 Battery Calibration (Conditioning) ....................................................................................................................................................... 28 5.1 Selecting a Battery to be Calibrated ................................................................................................................................................. 28 5.2 Initiating Calibration of Selected Battery .......................................................................................................................................... 28 5.3 Terminating Calibration of Selected Battery ..................................................................................................................................... 28 6 MODE Pin Operation ............................................................................................................................................................................ 29 6.1 Stand Alone Charge Indication ......................................................................................................................................................... 29 6.2 Hardware Charge Inhibit .................................................................................................................................................................. 29 6.3 Charging When SCL and SDA are Low ............................................................................................................................................ 29 6.4 Charging With an SMBus Host ........................................................................................................................................................ 29 7 Battery Charger Controller ................................................................................................................................................................... 29 7.1 Charge MUX Switches ..................................................................................................................................................................... 30 7.2 Dual Charging .................................................................................................................................................................................. 30 8 PowerPath Controller .......................................................................................................................................................................... 31 8.1 Autonomous PowerPath Switching ................................................................................................................................................. 31 8.2 Short-Circuit Protection ................................................................................................................................................................... 31 8.3 Emergency Turn-Off ........................................................................................................................................................................ 32 8.4 Power-Up Strategy .......................................................................................................................................................................... 32 9 The Voltage DAC Block ........................................................................................................................................................................ 32 10 The Current DAC Block ........................................................................................................................................................................ 32
12
UU
(For Operation Section)
1760f
LTC1760
OPERATIO
1 Overview The LTC1760 is composed of an SMBus interface with dual port capability, a sequencer for managing system power and the charging and discharging of two batteries, a battery charger controller, charge mux controller, powerpath controller, a 10-bit current DAC (IDAC) and 11-bit voltage DAC (VDAC). When coupled with optional system software for generating composite battery information, it forms a complete Smart Battery System Manager for charging and selecting two smart batteries. The battery charger is controlled by the sequencer which uses the level 3 SMBus interface to read ChargingVoltage(), Voltage(), ChargingCurrent(), Current(), Alarm() and BatteryMode(). This information, together with thermistor measurements allows the sequencer to select the charging battery and safely servo on voltage and current. Charging can be accomplished only if the voltage at DCDIV indicates that sufficient voltage is available from the input power source, usually an AC adapter. The charge mux, which selects the battery to be charged, is capable of charging both batteries simultaneously. The charge mux switch drivers are configured to allow charger current to share between the two batteries and to prevent current from flowing in a reverse direction in the switch. The amount of current that each battery receives will depend upon the relative capacity of each battery and the battery voltage. This can result in significantly shorter charging times (up to 50% for Li-Ion batteries) than sequential charging of each battery. The sequencer also selects which of the pairs of PFET switches will provide power to the system load. If the system voltage drops below the threshold set by the LOPWR resistor divider, then all of the output-side PFETs are turned on quickly. The input-side PFETs act as diodes in this mode and power is taken from the highest voltage source available at the DCIN, BAT1, or BAT2 inputs. The input-side powerpath switch driver that is delivering power then closes its input switch to reduce the power dissipation in the PFET bulk diode. In effect, this system provides diode-like behavior from the FET switches, without the attendant high power dissipation from diodes. The HOST is informed of this 3-Diode mode status when it polls the powerpath status register via the SMBus interface. High speed powerpath switching at the LOPWR trip point is handled autonomously. Simultaneous discharge of both batteries is supported. The switch drivers prevent reverse current flow in the switches and automatically discharge both batteries into the load, sharing current according to the relative capacity of the batteries. Simultaneous dual discharge can increase battery operating time by up to 10% by reducing losses in the switches and reducing internal battery losses associated with high discharge rates. 2 The SMBus Interface 2.1 SMBus Interface Overview The SMBus interface allows the LTC1760 to communicate with two batteries and the SMBus Host. The SMBus Interface supports true dual port operation by allowing the SMBus Host to be connected to the SMBus of either battery. The LTC1760 is able to operate as an SMBus master or slave device. References: Smart Battery System Manager Specification: Revision 1.1, SBS Implementers Forum. Smart Battery Data Specification: Revision 1.1, SBS Implementers Forum. Smart Battery Charger Specification: Revision 1.1, SBS Implementers Forum System Management Bus Specification: Revision 1.1, SBS Implementers Forum I2C-Bus and How to Use it: V1.0, Philips Semiconductor.
U
(Refer to Block Diagram and Typical Application Figure)
1760f
13
LTC1760
OPERATIO
2.2 Data Bit Definition of Supported SMBus Functions.
Function BatterySystemState() LTC1760 SMBus Mode Access Slave Read/ Write SMBus Address 7'b0001_010 Command Code 8'h01 Data Type Status/ Control Data Bit or Nibble Definition/Allowed Values (See section 2.3 for Details)
D15 D14 D13 D12 D11 D10 D09 D08 D07 D06 D05 D04 D03 D02 D01 D00
POWER_BY_BAT4
POWER_BY_BAT3
POWER_BY_BAT2
POWER_BY_BAT1
PRESENT_ BAT2 POWER_NOT_GOOD
1
0 BatterySystemStateCont() Slave Read/ Write 7'b0001_010 8'h02 Status/ Control
0 0/1 0/1 0
0 0/1 0/1 0
0 0/1 0/1 0
0 0/1 0/1
CALIBRATE_REQUEST_SUPPORT
0
CALIBRATE_REQUEST
CHARGING_INHIBIT
CALIBRATE_BAT4
CALIBRATE_BAT3
CALIBRATE_BAT2
CALIBRATE_BAT1
CHARGER_POR
0 BatterySystemInfo() Slave Read 7'b0001_010 8'h04 Status
0
0
0
0
0 0/1 0/1 0 0/1 0/1 0/1 0/1 1 0/1 0/1 BATTERY SYSTEM REVISION 0 1 0 0 0 BATTERY SUPPORTED 0 1
RESERVED 0 LTC() Slave Read/ Write 7'b0001_010 8'h3c Status/ Control 0 0 0
RESERVED 0 0 0
LTC_VERSION3
LTC_VERSION2
0
LTC_VERSION1
0
0/1 0 BatteryMode() Master Read 7'b0001_011 8'h03 Status
0
0
0
0
0
1 0/1 0
0
0
0
CONDITION_FLAG
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1
1760f
14
RESERVED
LTC_VERSION0
1
POWER_OFF
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
TURBO
AC_PRESENT
CALIBRATE
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
PRESENT_ BAT1
PRESENT_ BAT4
PRESENT_ BAT3
CHARGE_BAT4
CHARGE_BAT3
CHARGE_BAT2
CHARGE_BAT1
SMB_BAT4
SMB_BAT3
SMB_BAT2
SMB_BAT1
U
LTC1760
OPERATIO
Function Current()
IA15
IA14
IA13
IA12
IA11
IA10
IA09
IA08
IA07
IA06
IA05
IA04
IA03
IA02 VA02 IR02 VR02 RESERVED ARA_ADD02
1
IA01 VA01 IR01 VR01 RESERVED ARA_ADD01
0
0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 Voltage() Master Read 7'b0001_011 8'h09 Value
VA15
VA14
VA13
VA12
VA11
VA10
VA09
VA08
VA07
VA06
VA05
VA04
VA03
0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 ChargingCurrent() Master Read 7'b0001_011 8'h14 Value
IR15
IR14
IR13
IR12
IR11
IR10
IR09
IR08
IR07
IR06
IR05
IR04
IR03
0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 ChargingVoltage() Master Read 7'b0001_011 8'h15 Value
VR15
VR14
VR13
VR12
VR11
VR10
VR09
VR08
VR07
VR06
VR05
VR04
VR03
0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 AlarmWarning () Master 7'b0001_011 8'h16 Status
TERMINATE_DISCHARGE_ALARM
TERMINATE_CHARGE_RESERVED
TERMINATE_CHARGE_ALARM
OVER_TEMP_ALARM
FULLY_DISCHARGED
OVER_CHARGED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
Read AlertResponse () see (1) Slave Read Byte 7'b0001_100 N/A Register
0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1
ARA_ADD07
ARA_ADD06
ARA_ADD05
ARA_ADD04
ARA_ADD03
0 (1) Read-byte format. 'h14 is returned as the interrupt address of the LTC1760.
0
0
1
0
1760f
15
ARA_ADD00
0
RESERVED
VR00
IR00
VA00
IA00
U
LTC1760 Mode Access Master Read SMBus Address 7'b0001_011 Command Code 8'h0a Data Type Value Data Bit or Nibble Definition/Allowed Values (See section 2.3 for Details)
D15 D14 D13 D12 D11 D10 D09 D08 D07 D06 D05 D04 D03 D02 D01 D00
LTC1760
OPERATIO
2.3 Description of Supported SMBus Functions The functions are described as follows: Function Name() (command code) Description: A brief description of the function. Purpose: The purpose of the function, and an example where appropriate. SMBus Protocol: Refer to Section 2.5 and to the SMBus specification for more details. Input, Output or Input/Output: A description of the data supplied to, or returned by, the function. Whenever the LTC1760 encounters a valid command with invalid data, it ACK's the command, and ignores the invalid data. For example, if an attempt is made to select battery A and B to simultaneously communicate with the system host, the LTC1760 will just ignore the request. 2.3.1 BatterySystemState() ('h01) Description: This function returns the present state of the LTC1760 and allows access to individual batteries. The information is broken into four nibbles that report: Which battery is communicating with the SMBus Host Which battery(s), if any, or AC is powering the system Which battery(s) is connected to the Smart Charger Which battery(s) is present. The LTC1760 provides a mechanism to notify the system whenever there is a change in its state. Specifically, the LTC1760 provides the system with a notification whenever: * A battery is added or removed (Polling or SMBALERT). * AC power is connected or disconnected (Polling or SMBALERT). * The LTC1760 autonomously changes the configuration of the battery(s) supplying power (Polling only).
16
U
* The LTC1760 autonomously changes the configuration of the battery(s) being charged (Polling only). Purpose: Used by the SMBus Host to determine the present state of the LTC1760 and the attached batteries. It also may be used to determine the state of the battery system after the LTC1760 notifies the SMBus Host of a change via SMBALERT. SMBus Protocol: Read or Write Word. Input/Output: word - Refer to "Section 2.2" for bit mapping. SMB_BAT[4:1] The read/write SMB_BAT[4:1] nibble is used by the SMBus Host to select with which individual battery to communicate or to determine with which individual battery it is communicating. For example, an application that displays the remaining capacity of all batteries would write to this nibble to individually select each battery in turn and get its capacity. Allowed values are: 'b0010: SMBus Host is communicating with Battery 2. 'b0001: SMBus Host is communicating with Battery 1. (Power On Reset Value) To change this nibble, set only one of the lower two bits of this nibble high. All other values will simply be ignored. POWER_BY_BAT[4:1] The read only POWER_BY_BAT[4:1] nibble is used by the SMBus Host to determine which battery(s) is powering the system. All writes to this nibble will be ignored. Allowed values are: 'b0011: System being powered by Battery 2 and Battery 1 simultaneously. 'b0010: System being powered by Battery 2. 'b0001: System being powered by Battery 1. 'b0000: System being powered by AC.
1760f
LTC1760
OPERATIO
CHARGE_BAT[4:1] The read only CHARGE_BAT[4:1] nibble is used by the SMBus Host to determine which, if any, battery is being charged. All writes to this nibble will be ignored. Allowed values are: 'b0011: Battery 2 and Battery 1 being charged. 'b0010: Battery 2 is being charged. 'b0001: Battery 1 is being charged. 'b0000: No Battery being charged. An indication that multiple batteries are being charged simultaneously does not indicate that the batteries are being charged at the same rate or that they will complete their charge at the same time. To actually determine when an individual battery will be fully charged, use the SMB_BAT[4:1] nibble to individually select the battery of interest and read the TimeToFull() value. PRESENT_BAT[4:1] The read only PRESENT_BAT[4:1] nibble is used by the SMBus Host to determine how many and which batteries are present. All writes to this nibble will be ignored. Allowed values are: 'b0011: Battery 2 and Battery 1 are present. 'b0010: Battery 2 is present. 'b0001: Battery 1 is present. 'b0000: No batteries are present. 2.3.2 BatterySystemStateCont() ('h02) Description: This function returns additional state information of the LTC1760 and provides an interface to prohibit charging. This command also removes any requirement for the SMBus Host to communicate directly with the charger to obtain AC presence information. When the LTC1760 is used, access to the charger address, 'h12, is blocked.
U
Purpose: Used by the SMBus Host to retrieve additional state information from the LTC1760 and the overall system power configuration. It may also be used by the system to prohibit any battery charging. SMBus Protocol: Read or Write Word. Input/Output: word - Refer to "Section 2.2" for bit mapping AC_PRESENT Bit The read only AC_PRESENT bit is used to show the user the status of AC availability to power the system. It may be used internally by the SMBus Host in conjunction with other information to determine when it is appropriate to allow a battery conditioning cycle. Whenever there is a change in the AC status, the LTC1760 asserts SMBALERT low. In response, the system has to read this register to determine the actual presence of AC. The LTC1760 uses the DCDIV pin to measure the presence of AC. Allowed values are: 'b1: The LTC1760 has determined that AC is present. 'b0: The LTC1760 has determined that AC is not present. POWER_NOT_GOOD Bit The read only POWER_NOT_GOOD bit is used to show that the voltage delivered to the system load is inadequate. This is determined by the comparator on the LOPWR pin. Allowed values are: 'b1: The LTC1760 has determined that the voltage delivered to the system load is inadequate. 'b0: The LTC1760 has determined that the voltage delivered to the system load is adequate. CALIBRATE_REQUEST_SUPPORT Bit The read only CALIBRATE_REQUEST_SUPPORT bit is always set to indicate that the LTC1760 has a mechanism to determine when any of the attached batteries are in need of a calibration cycle.
1760f
17
LTC1760
OPERATIO
CALIBRATE_REQUEST Bit The read only CALIBRATE_REQUEST bit is set whenever the LTC1760 has determined that one or more of the connected batteries need a calibration cycle. Allowed values are: 'b1: The LTC1760 has determined that one or both batteries requires calibration. 'b0: The LTC1760 has determined that no batteries require calibration. CHARGING_INHIBIT Bit The read/write CHARGING_INHIBIT is used by the SMBus Host to inhibit charging or to determine if charging is inhibited. This bit is also set if MODE is used to inhibit charging. Allowed values are: 'b1: The LTC1760 must not allow any battery charging to occur. 'b0: The LTC1760 may charge batteries as needed, (Power On Reset Value). CHARGER_POR Bit The read/write CHARGER_POR bit is used to force a charger power on reset. Writing a 1 to this bit will cause a charger power on reset with the following effects. * Charging will be turned off and wake-up charging will be resumed. This is the same as if the batteries were removed and then reinserted. * The three minute wake-up watchdog timer will be restarted. Writing a 0 to this bit has no effect. A read of this bit always returns a 0. CALIBRATE Bit The read/write CALIBRATE bit is used either to show the status of battery calibration cycles in the LTC1760 or to begin or end a calibration cycle.
18
U
CALIBRATE_BAT[4:1] Nibble The read/write CALIBRATE_BAT[4:1] nibble is used by the SMBus Host to select the battery to be calibrated or to determine which individual battery is being calibrated. Allowed read values are: 'b0010: Battery 2 is being calibrated . CALIBRATE must be 1. 'b0001: Battery 1 is being calibrated. CALIBRATE must be 1. 'b0000: No batteries are being calibrated. Allowed write values are: 'b0010: Select Battery 2 for calibration. 'b0001: Select Battery 1 for calibration. 'b0000: Allow LTC1760 to choose battery to be calibrated. All other values will simply be ignored. This provides a mechanism to update the other BatterySystemStateCont() bits without altering this nibble. 2.3.3 BatterySystemInfo ()('h04) Description: The SMBus Host uses this command to determine the capabilities of the LTC1760. Purpose: Allows the SMBus Host to determine the number of batteries the LTC1760 supports as well as the specification revision implemented by the LTC1760. SMBus Protocol: Read Word Input/Output: word -- Refer to "Section 2.2" for bit mapping. BATTERIES_SUPPORTED Nibble The read only BATTERIES_SUPPORTED nibble is used by the SMBus Host to determine how many batteries the LTC1760 can support. The two-battery LTC1760 always returns 'b0011 for this nibble.
1760f
LTC1760
OPERATIO U
2.3.5 BatteryMode() ('h03) Description: This function is used by the LTC1760 to read the Battery Mode register. Purpose: Allows the LTC1760 to determine if a battery requires a conditioning/calibration cycle. SMBus Protocol: Read Word. LTC1760 reads Battery 1 or Battery 2 as an SMBus Master. Input/Output: word -- Refer to "Section 2.2" for bit mapping. CONDITION_FLAG Bit The CONDITION_FLAG bit is set whenever the battery requires calibration. Allowed values: 'b1 - Battery requires calibration. (Also known as a Condition Cycle Request). 'b0 - Battery does not require calibration. 2.3.6 Voltage() ('h09) Description: This function is used by the LTC1760 to read the actual cell-pack voltage . Purpose: Allows the LTC1760 to determine the cell pack voltage and close the charging voltage servo loop. SMBus Protocol: Read Word. LTC1760 reads Battery 1 or Battery 2 as an SMBus Master. Output: unsigned integer -- battery terminal voltage in milli-volts. Refer to "Section 2.2" for bit mapping. Units: mV. Range: 0 to 65,535 mV.
1760f
BATTERY_SYSTEM_REVISION Nibble The read only BATTERY_SYSTEM_REVISION nibble reports the version of the Smart Battery System Manager specification supported. LTC1760 returns 'b1000 for this nibble, indicating Version 1.0 without optional PEC support. 2.3.4 LTC() ('h3c) Description: This function returns the LTC Version nibble and allows the user to perform expanded Smart Battery System Manager functions. Purpose: Used by the SMBus Host to determine the version of the LTC1760 and to program and monitor TURBO and POWER_OFF special functions. SMBus Protocol: Read or Write Word. Input/Output: word -- Refer to "Section 2.2" for bit mapping. POWER_OFF Bit This read/write bit allows the LTC1760 to turn off all power path sources. Allowed values: 'b1: All power path sources are off. 'b0: All power path sources are enabled. (Power On Reset Value). TURBO Bit This read/write bit allows the LTC1760 to enter TURBO charging mode. Allowed values: 'b1: Turbo Charging mode enabled. 'b0: Turbo Charging mode disabled. (Power On Reset Value). LTC_Version[3:0] Nibble This read only nibble always returns 'b0001 as the LTC1760 version.
19
LTC1760
OPERATIO
Description:
2.3.7 Current() ('h0a) This function is used by the LTC1760 to read the actual current being supplied through the battery terminals. Purpose: Allows the LTC1760 to determine how much current a battery is receiving through its terminals and close the charging current servo loop. SMBus Protocol: Read Word. LTC1760 reads Battery 1 or Battery 2 as an SMBus Master. Output: signed integer (2's complement) -- charge/discharge rate in mA increments - positive for charge, negative for discharge. Refer to "Section 2.2" for bit mapping. Units: mA. Range: 0 to 32,767 mA for charge or 0 to -32,768 mA for discharge. 2.3.8 ChargingCurrent() ('h14) Description: This function is used by the LTC1760 to read the Smart Battery's desired charging current. Purpose: Allows the LTC1760 to determine the maximum charging current. SMBus Protocol: Read Word. LTC1760 reads Battery 1 or Battery 2 as an SMBus Master. Output: unsigned integer -- maximum charger output current in mA. Refer to "Section 2.2" for bit mapping. Units: mA. Range: 0 to 65,534 mA. 2.3.9 ChargingVoltage() ('h15) Description: This function is used by the LTC1760 to read the Smart Battery's desired charging voltage.
20
U
Purpose: Allows the LTC1760 to determine the maximum charging voltage. SMBus Protocol: Read Word. LTC1760 reads Battery 1 or Battery 2 as an SMBus Master. Output: unsigned integer -- charger output voltage in mV. Refer to Section 2.2 for bit mapping. Units: mV. Range: 0 to 65,534 mV. 2.3.10 AlarmWarning () ('h16) Description: This function is used by the LTC1760 to read the Smart Battery alarm register. Purpose: Allows the LTC1760 to determine the state of all applicable alarm flags. SMBus Protocol: Read Word. LTC1760 reads Battery 1 or Battery 2 as an SMBus Master. Output: unsigned integer - Refer to "Section 2.2" for bit mapping. OVER_CHARGED_ALARM Bit The read only OVER_CHARGED_ALARM bit is used by the LTC1760 to determine if charging may continue. Allowed values are: 'b1: The LTC1760 will not charge this battery. 'b0: The LTC1760 may charge this battery if other conditions permit charging. TERMINATE_CHARGE_ALARM Bit The read only TERMINATE_CHARGE_ALARM bit is used by the LTC1760 to determine if charging may continue. Allowed values are: 'b1: The LTC1760 will not charge this battery. 'b0: The LTC1760 may charge this battery if other conditions permit charging.
1760f
LTC1760
OPERATIO U
'b0: The LTC1760 may continue discharging this battery. 2.3.11 AlertResponse () Description: The SMBus Host uses the Alert Response Address (ARA) to quickly identify the generator of an SMBALERT# event. Purpose: The LTC1760 will respond to an ARA if the SMBALERT signal is actively pulling down the SMBALERT# bus. The LTC1760 will follow the prioritization reporting as defined in the "System Management Bus Specification". SMBus Protocol: A 7-bit Addressable Device Responds to an ARA. Output: The device address will be sent to the SMBus Host. The LTC1760 device address is 0x14 (or 0x0a if just looking at the 7 bit address field). The following events will cause the LTC1760 to pull-down the SMBALERT# bus through the SMBALERT pin: * Change of AC_PRESENT in the BatterySystemStateCont() function. * Change of BATTERY_PRESENT in the BatterySystemState() function. * Internal power on reset condition. Refer to "Section 2.2" for bit mapping. 2.4 SMBus Dual Port Operation The SMBus Interface includes the LTC1760's SMBus controller, as well as circuitry to arbitrate and connect the battery and SMBus Host interfaces. The SMBus controller generates and interprets all LTC1760 SMBus functions. The dual port operation allows the SMBus Host to be connected to the SMBus of either battery by setting the SMB_BAT[4:1] nibble. Arbitration is handled by stretching an SMBus start sequence when a bus collision might occur. Whenever configurations are switched, the LTC1760 will generate a harmless SMBus reset on SMB1 and SMB2 as required. The four possible configurations are illustrated in Figure 1. Sample SMBus communications are shown in Figures 2 and 3.
1760f
TERMINATE_CHARGE_RESERVED Bit The read only TERMINATE_CHARGE_RESERVED bit is used by the LTC1760 to determine if charging may continue. Allowed values are: 'b1: The LTC1760 will not charge this battery. 'b0: The LTC1760 may charge this battery if other conditions permit charging. OVER_TEMP_ALARM Bit The read only OVER_TEMP_ALARM is used by the LTC1760 to determine if charging may continue. Allowed values are: 'b1: The LTC1760 will not charge this battery. 'b0: The LTC1760 may charge this battery if other conditions permit charging. TERMINATE_DISCHARGE_ALARM Bit The read only TERMINATE_DISCHARGE_ALARM bit is used by the LTC1760 to determine if discharge from the battery is still allowed. This is used for power path management and battery calibration. Allowed values are: 'b1: The LTC1760 will terminate calibration and should try to not use this battery in the power path. When all other power paths fail the LTC1760 will ignore this alarm and still try to supply system power from this source. 'b0: The LTC1760 may continue discharging this battery. FULLY_DISCHARGED Bit The read only FULLY_DISCHARGED bit is used by the LTC1760 to determine if discharge from the battery is still allowed. This is used for power path management and battery calibration. Allowed values are: 'b1: The LTC1760 will terminate calibration and should try to not use this battery in the power path. When all other power paths fail the LTC1760 will ignore this alarm and still try to supply system power from this source.
21
LTC1760
OPERATIO
HOST
SMB*
LTC1760 SMBus CONTROLLER
HOST, LTC1760 AND BAT1 CAN COMMUNICATE. BAT2 ORIGINATED COMMANDS ARE IGNORED.
HOST
SMB*
LTC1760 SMBus CONTROLLER
HOST, LTC1760 AND BAT2 CAN COMMUNICATE. BAT1 ORIGINATED COMMANDS ARE IGNORED.
*SMB INCLUDES SCL AND SDA, SMB1 INCLUDES SCL1 AND SDA1, AND SMB2 INCLUDES SCL2 AND SDA2.
Figure 1. Switch Configurations Used by the LTC1760 for Managing Dual Port Battery Communication
2.5 LTC1760 SMBus Controller Operation SMBus communication with the LTC1760 is handled by the SMBus Controller, a sub-block of the SMBus Interface. Data is clocked into the SMBus Controller block shift register after the rising SCL edge. Data is clocked out of the SMBus Control block shift register after the falling edge of SCL. The LTC1760 acting as a slave will acknowledge (ACK) each byte of serial data. The Command byte will be NACKed if an invalid command code is transmitted to the LTC1760. The SMBus Controller must respond if addressed as a combined Smart Battery System Manager (Address 14). A valid address includes a legal Read/Write bit. The SMBus Controller will ignore invalid data although
22
U
SMB2* BAT2 HOST SMB1* SMB2* SMB* BAT2 BAT1 SMB1* LTC1760 SMBus CONTROLLER BAT1 LTC1760 AND BAT2 CAN COMMUNICATE. HOST AND BAT1 ORIGINATED COMMANDS ARE STRETCHED IF THE LTC1760 IS COMMUNICATING WITH BAT2.
(1a)
(1b)
SMB2*
BAT2 HOST
SMB2* SMB*
BAT2
SMB1*
BAT1
SMB1* LTC1760 SMBus CONTROLLER
BAT1
LTC1760 AND BAT1 CAN COMMUNICATE. HOST AND BAT2 ORIGINATED COMMANDS ARE STRETCHED IF THE LTC1760 IS COMMUNICATING WITH BAT1.
(1c)
(1d)
1760 F01
the data transmission with the invalid data will still be ACK'ed. When the LTC1760, acting as a bus master receives a NACK, it will terminate the transmission and provide a STOP condition on the bus. Detection of a STOP condition, power on reset, or SMBus time-out will reset the controller to an initial state at any time. The LTC1760 supports ARA, Word Write and Word Read protocols as an SMBus slave. The LTC1760 supports Word Read protocol as an SMBus master. Refer to "System Management Bus Specification" for complete description of required operation and symbols.
1760f
SMBus DUAL PORT
SCL
SDA
SCL1
SDA1
SCL2
SDA2
Figure 2. LTC1760 Stretches Host's Communication With Battery 1 While It Completes a Read Of Battery 2. (Configuration b)
SMBus DUAL PORT
SCL
SDA
SCL1
SDA1
SCL2
SDA2
Figure 3. LTC1760 Queries Battery 1 Followed By Battery 2 For Requested Current. (Configuration b)
U
OPERATIO
LTC1760
23
1760f
LTC1760
OPERATIO
2.6 LTC1760 SMBALERT Operation The SMBALERT pin allows the LTC1760 to signal to the SMBus Host that there has been a change of status. This pin is asserted low whenever there is a change in battery presence, AC presence or after a power on reset event. This pin is cleared during an Alert Response or any of the following reads: BatterySystemState(),BatterySystemStateCont(), BatterySystemInfo(), or LTC(). 3 Charging Algorithm Overview 3.1 Wake-Up Charging Initiation The following conditions must be met in order to allow wake-up charging: 1. The battery thermistor must be COLD-RANGE, IDEALRANGE, or UNDER-RANGE. 2. AC must be present. 3. BatterySystemStateCont(CHARGING_INHIBIT) must be de-asserted (or low). 4. Hardware controlled charging inhibit must be de-asserted (MODE not low with VDDS high). Wake-up charging initiates when a newly inserted battery does not respond to any LTC1760 master read commands. Only one battery will wake-up charge at a time. When two batteries are inserted and both require wake-up charging, Battery 1 will wake-up charge first. Battery 2 will only wake-up charge when Battery 1 terminates wake-up charging. Wake-up charging takes priority over controlled charging; this prevents one battery from tying up the charger when it would be advantageous to dual charge two deeply discharged batteries. The LTC1760 will attempt to reinitiate wake-up charging on both batteries after the SMBus Host asserts BatterySystemStateCont(CHARGER_POR) or a power on reset event. This will reset any wake-up charging safety timers and is equivalent to removing and reinserting both batteries. The LTC1760 will attempt to reinitiate wake-up charging on a battery if the battery is not being charged, the
24
U
thermistor is reporting IDEAL-RANGE, and the battery fails to respond to an SMBus query. This is an important feature for handling deeply discharged NiMh batteries. These batteries may begin to talk while being charged and go silent once charging has stopped. Wake-up charging is disabled if the battery thermistor is COLD-RANGE or UNDER-RANGE and the battery has been charged for longer than tTIMEOUT. 3.2 Wake-Up Charging Termination The LTC1760 will terminate wake-up charging when any of the following conditions are met: 1. Battery removal (thermistor indicating OVER-RANGE) 2. AC is removed. 3. The SMBus Host issues a calibration request by setting BatterySystemStateCont(CALIBRATE) high. 4. Any response to an LTC1760 master read of ChargingCurrent(), Current(), ChargingVoltage(), or Voltage(). Note that the LTC1760 ignores all writes from the battery. 5. Any of the following AlarmWarning() bits asserted high: OVER_CHARGED_ALARM TERMINATE_CHARGE_ALARM TERMINATE_CHARGE_RESERVED OVER_TEMP_ALARM Note that the LTC1760 ignores all writes from the battery. Each battery's charge alarm is cached inside the LTC1760. This bit will be set when any of the upper four bits of the battery's AlarmWarning() response are set. This bit will remain set if a subsequent AlarmWarning() fails to respond. The cached alarm will be cleared by any of the following conditions. a) Associated battery is removed. b) A subsequent AlarmWarning() clears all charge alarm bits for the associated battery. c) A power on reset event. d) The SMBus Host asserts BatterySystemStateCont(CHARGER_POR) high.
1760f
LTC1760
OPERATIO
6. An SMBus Host write asserts the LTC1760 BatterySystemStateCont(CHARGING_INHIBIT) high. 7. Hardware controlled charging inhibit is asserted (MODE low with VDDS high). 8. The thermistor of the battery being charged indicates COLD-RANGE and the battery has been charged for longer than tTIMEOUT. 9. The thermistor of the battery being charged indicates UNDER-RANGE and the battery has been charged for longer than tTIMEOUT. 10. The thermistor of the battery being charged indicates HOT-RANGE. 11. Any SMBus communication line is grounded for longer than tQUERY. 12. BatterySystemStateCont(POWER_NOT_GOOD) is high. 13. The emergency off feature has been asserted using the DCDIV input pin. 3.3 Wake-Up Charging Current and Voltage Limits The wake-up charging current is fixed at IWAKE-UP for all values of ILIMIT. Wake-up charging uses the low current mode described in "Section 10". The wake-up charging voltage is not limited by the VLIMIT function. 3.4 Controlled Charging Initiation All of the following conditions must be met in order to allow controlled charging of a given battery. One or both batteries may be control charged at a time. 1. The battery thermistor must be COLD-RANGE, IDEALRANGE, or UNDER-RANGE. 2. AC must be present. 3. BatterySystemStateCont(CHARGING_INHIBIT) must be de-asserted (or low). 4. Hardware controlled charging inhibit must be de-asserted (MODE not low with VDDS high).
U
5. The battery responds to an LTC1760 master read of Alarm() with all charge alarms deasserted. 6. The battery responds to an LTC1760 master read of ChargingVoltage() with a non zero voltage request value. 7. The battery responds to an LTC1760 master read of Voltage(). 8. The battery responds to an LTC1760 master read of ChargingCurrent() with a non zero current request value. 9. The battery responds to an LTC1760 master read of Current(). The following charging related functions are polled each t QUERY : Alarm(), ChargingVoltage(), Voltage(), ChargingCurrent(), and Current(). 3.5 Controlled Charging Termination The LTC1760 will terminate controlled charging when any of the following conditions are met: 1. Battery removal, or thermistor indicating OVER-RANGE. 2. AC removal. 3. The SMBus Host issues a calibration request by setting BatterySystemStateCont(CALIBRATE) high. 4. An LTC1760 master read of ChargingCurrent() returning a zero current request. 5. An LTC1760 master read of ChargingVoltage() returning a zero voltage request. 6. Any of the following AlarmWarning() bits asserted high: OVER_CHARGED_ALARM TERMINATE_CHARGE_ALARM TERMINATE_CHARGE_RESERVED OVER_TEMP_ALARM Note that the LTC1760 ignores all writes from the battery. Each battery's charge alarm is cached inside the LTC1760. This bit will be set when any of the upper four bits of the battery's AlarmWarning() response are set.
1760f
25
LTC1760
OPERATIO
This bit will remain set if a subsequent AlarmWarning() fails to respond. The cached alarm will be cleared by any of the following conditions. a) Associated battery is removed. b) A subsequent AlarmWarning() clears all charge alarm bits for the associated battery. c) A power on reset event. d) The SMBus Host asserts BatterySystemStateCont(CHARGER_POR) high. 7. An SMBus Host write asserts the LTC1760 BatterySystemStateCont(CHARGING_INHIBIT) high. 8. Hardware controlled charging inhibit is asserted (MODE low with VDDS high). 9. The SMBus of the battery being charged has stopped acknowledging SMBus read commands for longer than tTIMEOUT. 10. The thermistor of the battery being charged indicates HOT-RANGE. 11. Any SMBus communication line is grounded for longer than tQUERY. 12. BatterySystemStateCont(POWER_NOT_GOOD) is high. 13. The emergency off feature has been asserted using the DCDIV input pin. Whenever changing conditions cause either battery to stop charging, charging is stopped immediately for all batteries and the voltage and current algorithms are reset to zero. Charging is not resumed until all the conditions for controlled charging are met. 3.6 Controlled Charging Current and Voltage Programming The LTC1760 monitors the requested and actual current in each battery and increases the programmed current unless one of the following conditions is met: a) The actual current exceeds the requested current in either battery.
26
U
b) The total programmed current equals the maximum of the two requested currents + ILIMIT/32 and LTC(TURBO) is de-asserted (or low). c) Only one battery is charging and the programmed current equals the requested current + ILIMIT/32. d) The total programmed current equals ILIMIT. The programmed current is updated every tQUERY. It is changed by the difference between the actual and requested currents. LTC(TURBO) provides a mechanism for the SMBus Host to put additional current into both batteries. Normally the LTC1760 will limit the current into both batteries to the maximum of the two requested currents + ILIMIT/32. When LTC(TURBO) is asserted, this restriction is removed, allowing the charger to output as much as ILIMIT into both batteries. Whenever changing conditions cause either battery to stop charging, the current algorithm is reset to zero. The LTC1760 monitors the requested and actual voltages in each battery and increases the programmed voltage by 16mV each tQUERY unless one of the following conditions are met: a) The actual voltage exceeds the requested voltage in either battery. b) The actual voltage exceeds VLIMIT. This is an extremely important feature of the LTC1760 since it allows the charger to servo on the internal cell voltage of the battery as determined by the Smart Battery. This voltage may be significantly lower than the battery pack terminal voltage which is used by all Level 2 chargers. The advantage for the LTC1760 is improved charge time, safety, and a more completely charged battery. The voltage correction cannot exceed the minimum requested voltage by more than 512mV. When decrementing, the programmed voltage is reduced by 16mV each tQUERY. Whenever changing conditions cause either battery to stop charging, the voltage algorithm is reset to zero.
1760f
LTC1760
OPERATIO
4 System Power Management Algorithm and Battery Calibration 4.1 Turning Off System Power The LTC1760 allows the user to turn off system power using the LTC(POWER_OFF) bit. When POWER_OFF is asserted high all power management functions are bypassed and the LTC1760 will turn off DCIN, BAT2 and BAT1 power paths. This feature allows the user to power down the system. Charging is still allowed when POWER_OFF is asserted high. 4.2 Power-By Algorithm When No Battery is Being Calibrated The LTC1760 will always attempt to maintain system power. The preferred configuration is to remain in 3- Diode mode. In 3-Diode mode, power will be provided by BAT1, BAT2 and DCIN with the source at the highest voltage potential automatically providing all the power. Sources at similar voltage potentials will share power based on their capacity. The following conditions will cause the LTC1760 to modify its preferred power-by algorithm. 1. A battery issues a terminate discharge alarm and AC_PRESENT is high. The LTC1760 will select the other battery and DCIN to power the system. 2. A battery issues a terminate discharge alarm and AC_PRESENT is low. The LTC1760 will select the other battery to power the system. 3. A battery issues a terminate discharge alarm, AC_PRESENT is low, and the other battery is not present or has previously alarmed. The LTC1760 will autonomously try to restore power by entering 3-Diode mode. The 3-Diode mode will ignore TERMINATE_DISCHARGE and FULLY_DISCHARGED alarms. 4.3 Power-By Algorithm When a Battery is Being Calibrated During battery calibration, the battery being calibrated is the only device powering the system. This will be reflected in the reported POWER_BY[4:1] bits. See "Section 5" for more information on battery calibration.
U
4.4 Power-By Reporting The following tables illustrate how BatterySystem State(POWER_BY_BAT[4:1]) interprets power path conditions.
Power Reporting for Batteries Being Calibrated
AC_PRESENT CALIBRATE_BAT2 CALIBRATE_BAT2 POWER_BY_BAT[4:1] 1 1 1 0 0 1 0 1 0 'b0000 'b0001 'b0010 *States not shown are not allowed
Power Reporting as a Function of Battery Presence
AC_PRESENT PRESENT_BAT2 PRESENT_BAT1 POWER_BY_BAT[4:1] 1 0 0 0 0 X 0 0 1 1 X 0 1 0 1 'b0000 'b0000 'b0001 'b0010 'b0011
Power Reporting with AC_PRESENT Low and both Batteries Present, as a Function of Power Alarms.
BATTERY 2 BATTERY 1 POWER ALARM POWER ALARM AC_PRESENT (NOTE 1) (NOTE 1) POWER_BY_BAT[4:1] 0 0 0 0 1 0 0 1 1 X 0 1 0 1 X 'b0011 'b0010 'b0001 'b0011 'b0000
Note 1: A power alarm means that ALARM() has returned TERMINATE_DISCHARGE=1 or FULLY_DISCHARGED_ALARM=1
Power Reporting When BatterySystemStateCont(POWER_NOT_GOOD) is High and the LTC1760 has Autonomously Entered 3-Diode Mode
AC_PRESENT PRESENT_BAT2 PRESENT_BAT1 POWER_BY_BAT[4:1] 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 'b0000 'b0001 'b0010 'b0011 'b0000 'b0000 'b0000 'b0000
1760f
27
LTC1760
OPERATIO
5 Battery Calibration (Conditioning) Calibration allows the SMBus Host to fully discharge a battery for conditioning purposes. The SMBus Host may determine the battery to be discharged or allow the LTC1760 to choose based on the batteries' request to be conditioned. 5.1 Selecting a Battery to be Calibrated Option 1) SMBus Host chooses battery to be calibrated using BatterySystemStateCont(CALIBRATE_BAT[4:1]) Allowed values: 'b0001: Set CALIBRATE_BAT1. Only has an effect if Battery 1 BatteryMode(CONDITION_FLAG) is high . May not be updated if a calibration is in progress. 'b0010: Set CALIBRATE_BAT2. Only has an effect if Battery 2 BatteryMode(CONDITION_FLAG) is high. May not be updated if a calibration is in progress. 'b0000: Clears CALIBRATE_BAT1 and CALIBRATE_BAT2 and allows LTC1760 to chose. Power on reset default. May not be updated if a calibration is in progress. Option 2) SMBus Host allows LTC1760 to choose battery to be calibrated. BatterySystemStateCont(CALIBRATE_BAT[4:1]) = 'b0000. See previous option. The LTC1760 determines that the battery requires calibration by reading BatteryMode(CONDITION_FLAG). This flag is cached in the LTC1760. The LTC1760 sets BatterySystemStateCont(CALIBRATE_REQUEST) high. The LTC1760 will always select the battery that is requesting calibration. If both batteries are requesting calibration, the LTC1760 will select Battery 1. If neither battery is requesting calibration, then calibration cannot occur.
28
U
5.2 Initiating Calibration of Selected Battery The SMBus Host initiates a calibration by writing to BatterySystemStateCont(CALIBRATE). Follow rules of the previous section to preserve battery intended for calibration. The SMBus Host must only set the calibration bit once per calibration. The LTC1760 will discharge the selected battery as long as the calibration is in progress (CALIBRATE high). Updates to the cached BatteryMode(CONDITION_FLAG) will be inhibited while CALIBRATE is asserted. This means that discharge of the battery will continue even if the battery clears the CONDITION_FLAG. 5.3 Terminating Calibration of Selected Battery Calibration will end when CALIBRATE is cleared. CALIBRATE will be cleared when: * AC is removed. * The battery being calibrated is removed. When the battery being calibrated is removed, the LTC1760 will automatically calibrate the other battery if it is requesting calibration. * BatterySystemStateCont(POWER_NOT_GOOD) is high. * The battery sets Alarm Warning (TERMINATE_DISCHARGE) high. * The battery sets Alarm Warning (FULLY_DISCHARGED) high. * A zero is written to the CALIBRATE bit. The LTC1760 will attempt to initiate a charge cycle after the discharge cycle is completed.
1760f
LTC1760
OPERATIO
6 MODE Pin Operation The MODE pin is a multifunction pin that allows the LTC1760 to: 1) display charging status in stand alone operation; 2) activate hardware charge inhibit; 3) charge when SCL and SDA are low and; 4) charge with an SMBus Host.
Summary of SDA, SCL and SMBALERT Operation as a Function of MODE and VDDS Levels
CONDITION VMODE = VVSS VVDDS < VILVDDS VMODE = VVSS VVDDS > VILVDDS VMODE = VVSS VVDDS < VILVDDS LTC1760 OPERATING MODE SCL: Clock for Status Indicators SDA: Battery 2 Status SMBALERT: Battery 1 Status SCL, SDA, SMBALERT: Normal Operation LTC1760 Charging Inhibited SCL, SDA Ignored and May Float Low SMBALERT: Normal Operation SCL1, SDA1, SCL2 and SDA2: Normal Operation and Charging is Allowed Normal Operation on all Pins, Charging is Allowed
VMODE = VVSS VVDDS > VILVDDS
6.1 Stand Alone Charge Indication When MODE is tied to GND and VVDDS < VIL_VDDS, the function of SDA, SMBALERT, and SCL are changed as described below. SDA is an output and is used to monitor charging status of Battery 2. Allowed valued are: Low: Battery 2 is charging. High: Battery 2 not charging (AC is not present or battery is not present). Blinking: Battery 2 charge complete (AC is present, battery is present and not charging). SMBALERT is used to monitor charging status of Battery1. Allowed valued are: Low: Battery 1 is charging. High: Battery 1 not charging (AC is not present or battery is not present). Blinking: Battery 1 charge complete (AC is present, battery is present and not charging).
U
SCL is an input and is used to determine the blinking rate of SDA and SMBALERT. Tie SCL high if blinking is not desired. This will provide two different states to indicate charging (output low) and not charging (output high). 6.2 Hardware Charge Inhibit When MODE is tied to GND and VVDDS>VIH_VDDS,charging is inhibited and BatterySystemStateCont(CHARGING_INHIBIT) will report a logic high. 6.3 Charging When SCL And SDA Are Low When MODE is tied to VCC2 and VDDS < VIL_VDDS, SDA and SCL are not used and will not interfere with LTC1760 battery communication. This feature allows the LTC1760 to autonomously charge when SCL and SDA are not available. This scenario might occur when SMBus Host has powered down and is no longer pulling up on SCL and SDA. 6.4 Charging With an SMBus Host When Mode is tied to VCC2 and VVDDS > VIL_VDDS, SDA and SCL are used to communicate with the SMBus Host. 7 Battery Charger Controller The LTC1760 charger controller uses a constant off-time, current mode step-down architecture. During normal operation, the top MOSFET is turned on each cycle when the oscillator sets the SR latch and turned off when the main current comparator ICMP resets the SR latch. While the top MOSFET is off, the bottom MOSFET is turned on until either the inductor current trips the current comparator IREV, or the beginning of the next cycle. The oscillator uses the equation. tOFF = (VDCIN - VBAT)/(VDCIN * fOSC) to set the bottom MOSFET on time. The result is quasiconstant frequency operation where the converter frequency remains nearly constant over a wide range of output voltages. This activity is diagrammed in Figure 4. The peak inductor current, at which ICMP resets the SR latch, is controlled by the voltage on ITH. ITH is in turn controlled by several loops, depending upon the situation
1760f
29
LTC1760
OPERATIO
OFF TGATE ON
ON BGATE OFF TRIP POINT SET BY ITH VOLTAGE INDUCTOR CURRENT
at hand. The average current control loop converts the voltage between CSP and BAT to a representative current. Error amp CA2 compares this current against the desired current programmed by the IDAC at the ISET pin and adjusts ITH for the desired voltage across RSENSE. The voltage at BAT is divided down by an internal resistor divider set by the VDAC and is used by error amp EA to decrease ITH if the divider voltage is above the 0.8V reference. The amplifier CL1 monitors and limits the input current, normally from the AC adapter, to a preset level (100 mV/ RCL). At input current limit, CL1 will decrease the ITH voltage and thus reduce battery charging current. An over-voltage comparator, OV, guards against transient overshoots (>7.5%). In this case, the top MOSFET is turned off until the over-voltage condition is cleared. This feature is useful for batteries which "load dump" themselves by opening their protection switch to perform functions such as calibration or pulse-mode charging. The top MOSFET driver is powered from a floating bootstrap capacitor C4. This capacitor is normally recharged from VCC through an external diode when the top MOSFET is turned off. As VIN decreases towards the selected battery voltage, the converter will attempt to turn on the top MOSFET continuously ("dropout''). A dropout timer detects this condition and forces the top MOSFET to turn off, and the bottom MOSFET on, for about 200ns at 40s intervals to recharge the bootstrap capacitor. 7.1 Charge MUX Switches The equivalent circuit of a charge MUX switch driver is shown in Figure 5. If the charger controller is not enabled, the charge MUX drivers will drive the gate and source of
30
U
DCIN + 10V (CHARGE PUMPED)
tOFF
TO BATTERY 1 FROM CHARGER
BAT1
-
CSN 35mV EAC
GCH1 Q3
+
SCH1 CC
+
20mV
-
10k Q4 OFF
Figure 4.
1760 F05
Figure 5. Charge MUX Switch Driver Equivalent Circuit
the series connected MOSFETs to a low voltage and the switch is off. When the charger controller is on, the charge MUX driver will keep the MOSFETs off until the voltage at CSN rises at least 35mV above the battery voltage. GCH1 is then driven with an error amplifier EAC until the voltage between BAT1 and CSN satisfies the error amplifier or until GCH1 is clamped by the internal Zener diode. The time required to close the switch could be quite long (many ms) due to the small currents output by the error amp and depending upon the size of the MOSFET switch. If the voltage at CSN decreases below VBAT1 - 20mV a comparator CC quickly turns off the MOSFETs to prevent reverse current from flowing in the switches. In essence, this system performs as a low forward voltage diode. Operation is identical for BAT2. 7.2 Dual Charging Note that the charge MUX switch drivers will operate together to allow both batteries to be charged simultaneously. If both charge MUX switch drivers are enabled, only the battery with the lowest voltage will be charged until its voltage rises to equal the higher voltage battery. The charge current will then share between the batteries according to the capacity of each battery. When batteries are controlled charging, only batteries with voltages above VCHMIN are allowed to charge. When a battery is wake-up charging this restriction does not apply.
1760f
LTC1760
OPERATIO U
8.1 Autonomous PowerPath Switching The LOPWR comparator monitors the voltage at the load through the resistor divider from pin SCN. If LTC (POWER_OFF) is low and the LOPWR comparator trips, then all of the switches are turned on (3-Diode mode) by the Autonomous PowerPath Controller to ensure that the system is powered from the source with the highest voltage. The Autonomous PowerPath Controller waits approximately 1second, to allow power to stabilize, and then reverts back to the PowerPath switch configuration requested by the PowerPath Management Algorithm. A power fail counter is incremented to indicate that a failure has occurred. If the power fail counter equals a value of 3, then the the Autonomous PowerPath Controller sets the switches to 3-Diode mode and BatterySystemStateCont(POWER_NOT_GOOD) will be set, provided the LOPWR comparator is still detecting a low power event. This is a three-strikes-and-you're-out process which is intended to debounce the POWER_NOT_GOOD indicator. The power fail counter is reset when battery or AC presence change. 8.2 Short-Circuit Protection Short-circuit protection operates in both a current mode and a voltage mode. If the voltage between SCP and SCN exceeds the short-circuit comparator threshold VTSC for more than 15ms, then all of the PowerPath switches are turned off and BatterySystemStateCont (POWER_NOT_GOOD) is set. Similarly, if the voltage at SCN falls below 3V for more than 15ms, then all of the PowerPath switches are turned off and POWER_NOT_GOOD is set high. The POWER_NOT_GOOD bit is reset by removing all power sources and allowing the voltage at VPLUS to fall below the UVLO threshold. If the POWER_NOT_GOOD bit is set, charging is disabled until VPLUS exceeds the UVLO threshold and the Charger Algorithm allows charging to resume. When a hard short-circuit occurs, it might pull all of the power sources down to near 0V potentials. The capacitors on VCC and VPLUS must be large enough to keep the circuit operating correctly during the 15ms short-circuit event. The charger will stop within a few microseconds, leaving a small current which must be provided by the capacitor on VPLUS. The recommended minimum values (1F on
1760f
OFF CP SWP GB1I EAP Q7 GB1O Q8 OFF CL RSC TO LOAD
1760 F06
8 PowerPath Controller The PowerPath switches are turned on and off by the power management algorithm. The external PFETs are usually connected as an input switch and an output switch. The output switch PFET is connected in series with the input PFET and the positive side of the short-circuit sensing resistor, RSC. The input switch is connected in series between the power source and the output PFET. The PowerPath switch driver equivalent circuit is shown in Figure 6. The output PFET is driven ON or OFF by the output side driver controlling pin GB10. The gate of the input PFET is driven by an error amplifier which monitors the voltage between the input power source (BAT1 in this case) and SCP. If the switch is turned off, the two outputs are driven to the higher of the two voltages present across the input/SCP terminals of the switch. When the switch is instructed to turn on, the output side driver immediately drives the gate of the output PFET approximately 6V below the highest of the voltages present at the input/SCP. When the output PFET turns on, the voltage at SCP will be pulled up to a diode drop below the source voltage by the bulk diode of the input PFET. If the source voltage is more than 25mV above SCP, EAP will drive the gate of the input PFET low until the input PFET turns on and reduces the voltage across the input/SCP to the EAP set point, or until the Zener clamp engages to limit the voltage applied to the input PFET. If the source voltage drops more than 20mV below SCP, then comparator CP turns on SWP to quickly prevent large reverse current in the switch. This operation mimics a diode with a low forward voltage drop.
20mV
- +
FROM BATTERY 1 BAT1
-
SCP
+
25mV
Figure 6. PowerPath Driver Equivalent Circuit
31
LTC1760
OPERATIO
VPLUS and 2F on VCC, including tolerances) should keep the LTC1760 operating above the UVLO trip voltage long enough to perform the short-circuit function when the input voltages are greater than 8V. Increasing the capacitor across VCC to 4.7F will allow operation down to the recommended 6V minimum. 8.3 Emergency Turn-Off All of the PowerPath switches can be forced off by setting the DCDIV pin to a voltage between 8V and 10V. This will have the same effect as a short-circuit event. DCDIV must be less than 5V and VPLUS must decrease below the UVLO threshold to re-enable the PowerPath switches. The LTC1760 can recover from this condition without removing power. Contact Applications Engineering for more information. 8.4 Power-Up Strategy All three PowerPath switches are turned on after VPLUS exceeds the UVLO threshold for more than 250ms. This delay is to prevent oscillation from a turn-on transient near the UVLO threshold. 9 The Voltage DAC Block The voltage DAC (VDAC) is a delta-sigma modulator which controls the effective value of an internal resistor, RVSET = 7.2k, used to program the maximum charger voltage. Figure 7 is a simplified diagram of the VDAC operation. The delta-sigma modulator and switch SWV convert the VDAC value to a variable resistance equal to (11/8)RVSET/(VDAC(VALUE)/2047). In regulation, VSET is servo driven to the 0.8V reference voltage, VREF.
CSN CB2 RVF 405.3k
VSET
CB1 VREF RVSET 7.2k SWV
Figure 7. Voltage DAC Operation
32
U
Capacitors CB1 and CB2 are used to average the voltage present at the VSET pin as well as provide a zero in the voltage loop to help stability and transient response time to voltage variations. 10 The Current DAC Block The current DAC is a delta-sigma modulator which controls the effective value of an internal resistor, RSET = 18.77k, used to program the maximum charger current. Figure 8 is a simplified diagram of the DAC operation. The delta-sigma modulator and switch convert the IDAC value to a variable resistance equal to 1.25RSET/ (IDAC(VALUE)/1023). In regulation, ISET is servo driven to the 0.8V reference voltage, VREF, and the current from RSET is matched against a current derived from the voltage between pins CSP and CSN. This current is (VCSP - VCSN)/ 3k. Therefore programmed current is: ICHG = 0.8 VREF 3k/(RSNS RSET) * (IDAC(VALUE)/1023) = (102.3mV/RSNS) * (IDAC(VALUE)/1023) During wake-up current operation, the current DAC enters a low current mode. The current DAC output is pulse-width modulated with a high frequency clock having a duty cycle value of 1/8. Therefore, the maximum output current provided by the charger is IMAX/8. The delta-sigma output gates this low duty cycle signal on and off. The delta-sigma shift registers are then clocked at a slower rate, about 40ms/bit, so that the charger has time to settle to the IMAX/8 value.
(VCSP - VCSN) 3k (FROM CA1 AMPLIFIER)
-
EA
ISET
TO ITH
+
TO ITH RSET 18.77k VREF
CSET
+
-
DAC VALUE (10 BITS)
1760 F08
MODULATOR
11
DAC VALUE (11 BITS)
1760 F07
MODULATOR
10
Figure 8. Current Dac Operation
1760f
LTC1760
APPLICATIO S I FOR ATIO
Automatic Current Sharing
In a dual parallel charge configuration, the LTC1760 does not actually control the current flowing into each individual battery. The capacity, or Amp-Hour rating, of each battery determines how the charger current is shared. This automatic steering of current is what allows both batteries to reach their full capacity points at the same time. In other words, given all other things equal, charge termination will happen simultaneously. A battery can be modeled as a huge capacitor and hence governed by the same laws. I = C * (dV/dt) where: I = The current flowing through the capacitor C = Capacity rating of battery (using amp-hour values instead of capacitance) dV = Change in voltage dt = Change in time The equivalent model of a set or parallel batteries is a set of parallel capacitors. Since they are in parallel, the change in voltage over change in time is the same for both batteries one and two. dV/dtBAT1 = dV/dtBAT2 From here we can simplify. IBAT1/CBAT1 = dV/dt = IBAT2/CBAT2 IBAT2 = IBAT1 CBAT2/CBAT1 At this point you can see that the current divides as the ratio of the two batteries capacity ratings. The sum of the current into both batteries is the same as the current being supply by the charger. This is independent of the mode of the charger (CC or CV). ICHRG = IBAT1 + IBAT2 From here we solve for the actual current for each battery. IBAT2 = ICHRG CBAT2/(CBAT1 + CBAT2) IBAT1 = ICHRG CBAT1/(CBAT1 + CBAT2) Please note that the actual observed current sharing will vary from manufacturer's claimed capacity ratings since it is actual physical capacity rating at the time of charge.
U
Capacity rating will change with age and use and hence the current sharing ratios can change over time. Adapter Limiting An important feature of the LTC1760 is the ability to automatically adjust charging current to a level which avoids overloading the wall adapter. This allows the product to operate at the same time that batteries are being charged without complex load management algorithms. Additionally, batteries will automatically be charged at the maximum possible rate of which the adapter is capable. This feature is created by sensing total adapter output current and adjusting charging current downward if a preset adapter current limit is exceeded. True analog control is used, with closed loop feedback ensuring that adapter load current remains within limits. Amplifier CL1 in Figure 9 senses the voltage across RCL, connected between the CLP and DCIN pins. When this voltage exceeds 100mV, the amplifier will override programmed charging current to limit adapter current to 100mV/RCL. A lowpass filter formed by 5k and 0.1F is required to eliminate switching noise. If the current limit is not used, CLP should be connected to DCIN.
100mV
W
UU
-
CL1
+
CLP 0.1F 5k AC ADAPTER INPUT VIN
1760 F09
+
DCIN RCL*
+
*RCL = 100mV ADAPTER CURRENT LIMIT CIN
Figure 9.
Setting Input Current Limit To set the input current limit, you need to know the minimum wall adapter current rating. Subtract 5% for the input current limit tolerance and use that current to determine the resistor value. RCL = 100mV/ILIM ILIM = Adapter Min Current - (Adapter Min Current * 5%)
1760f
33
LTC1760
APPLICATIO S I FOR ATIO
As is often the case, the wall adapter will usually have at least a +10% current limit margin and many times one can simply set the adapter current limit value to the actual adapter rating (see Table 1).
Table 1. Common RCL Resistor Values
Adapter Rating A 1.5 1.8 2 2.3 2.5 2.7 3 RCL Value* () 1% 0.06 0.05 0.045 0.039 0.036 0.033 0.030 RCL Power Dissipation (W) 0.135 0.162 0.18 0.206 0.225 0.241 0.27 RCL Power Rating (W) 0.25 0.25 0.25 0.25 0.5 0.5 0.5
*Values shown above are rounded to nearest standard value.
Extending System to More than 2 Batteries The LTC1760 can be extended to manage systems with more than 3 sources of power. Contact Linear Technology Applications Engineering for more information. Charge Termination Issues Batteries with constant-current charging and voltagebased charger termination might experience problems with reductions of charger current caused by adapter limiting. It is recommended that input limiting feature be defeated in such cases. Consult the battery manufacturer for information on how your battery terminates charging. Setting Charger Output Current Limit The LTC1760 current DAC and the PWM analog circuitry must coordinate the setting of the charger current. Failure to do so will result in incorrect charge currents.
Table 2. Recommended Resistor Values
IMAX (A) 1 2 3 4 RSENSE () 1% 0.100 0.05 0.025 0.025 RSENSE (W) 0.25 0.25 0.5 0.5 RILIM () 1% 0 10k 33k Open
Warning DO NOT CHANGE THE VALUE OF RILIM DURING OPERATION. The value must remain fixed and track the RSENSE value at all times. Changing the current setting can result
34
U
in currents that greatly exceed the requested value and potentially damage the battery or overload the wall adapter if no input current limiting is provided. Setting Charger Output Voltage Limit The value of an external resistor connected from the VLIMIT pin to GND determines one of five voltage limits that are applied to the charger output value. See Table 3. These limits provide a measure of safety with a hardware restriction on charging voltage, which cannot be overridden by software. This voltage sets the limit that will be applied to the battery as reported by battery. Since the battery internal voltage monitor point is the actual cell voltage, you may see higher voltages, up to 512mV higher, at the external charger terminals due to the voltage servo loop action. See Operations section 3.6 for more information on the voltage servo system.
Table 3. Recommended Resistor Values for RVLIM
VMAX Up to 8.4V Up to 12.6V Up to 16.8V Up to 21.0V Up to 32.7V (No Limit) RVLIM 1% 0 (Short to ground) 10k 33k 100k Open (or short to VCC2)
W
UU
Inductor Selection Higher operating frequencies allow the use of smaller inductor and capacitor values. A higher frequency generally results in lower efficiency because of MOSFET gate charge losses. In addition, the effect of inductor value on ripple current and low current operation must also be considered. The inductor ripple current IL decreases with higher frequency and increases with higher VIN.
IL =
( )( )
V VOUT 1 - OUT VIN fL 1
Accepting larger values of IL allows the use of low inductances, but results in higher output voltage ripple and greater core losses. A reasonable starting point for setting ripple current is IL = 0.4(IMAX). In no case should IL exceed 0.6(IMAX) due to limits imposed by IREV and
1760f
LTC1760
APPLICATIO S I FOR ATIO
CA1. Remember the maximum IL occurs at the maximum input voltage. In practice 10H is the lowest value recommended for use. Charger Switching Power MOSFET and Diode Selection Two external power MOSFETs must be selected for use with the LTC1760 charger: An N-channel MOSFET for the top (main) switch and an N-channel MOSFET for the bottom (synchronous) switch. The peak-to-peak gate drive levels are set by the VCC voltage. This voltage is typically 5.2V. Consequently, logiclevel threshold MOSFETs must be used. Pay close attention to the BVDSS specification for the MOSFETs as well; many of the logic level MOSFETs are limited to 30V or less. Selection criteria for the power MOSFETs include the "ON" resistance RDS(ON), reverse transfer capacitance CRSS, input voltage and maximum output current. The LTC1760 charger is always operating in continuous mode so the duty cycles for the top and bottom MOSFETs are given by: Main Switch Duty Cycle = VOUT/VIN Synchronous Switch Duty Cycle = (VIN - VOUT)/VIN The MOSFET power dissipations at maximum output current are given by: PMAIN = VOUT/VIN(IMAX) 2(1 + )RDS(ON) + k(VIN) 2 (IMAX)(CRSS)(f) PSYNC = (VIN - VOUT)/VIN(IMAX)2(1 + ) RDS(ON) Where is the temperature dependency of RDS(ON) and k is a constant inversely related to the gate drive current. Both MOSFETs have I2R losses while the topside N-channel equation includes an additional term for transition losses, which are highest at high input voltages. For VIN < 20V the high current efficiency generally improves with larger MOSFETs, while for VIN > 20V the transition losses rapidly increase to the point that the use of a higher RDS(ON) device with lower CRSS actually provides higher efficiency. The synchronous MOSFET losses are greatest at high input voltage or during a short-circuit when the duty cycle in this switch is nearly 100%. The term (1 + ) is generally given for a MOSFET in the form of a
U
normalized RDS(ON) vs Temperature curve, but = 0.005/C can be used as an approximation for low voltage MOSFETs. CRSS is usually specified in the MOSFET characteristics. The constant k = 1.7 can be used to estimate the contributions of the two terms in the main switch dissipation equation. If the LTC1760 charger is to operate in low dropout mode or with a high duty cycle greater than 85%, then the topside N-channel efficiency generally improves with a larger MOSFET. Using asymmetrical MOSFETs may achieve cost savings or efficiency gains. The Schottky diode D1, shown in the Typical Application, conducts during the dead-time between the conduction of the two power MOSFETs. This prevents the body diode of the bottom MOSFET from turning on and storing charge during the dead-time, which could cost as much as 1% in efficiency. A 1A Schottky is generally a good size for 4A regulators due to the relatively small average current. Larger diodes can result in additional transition losses due to their larger junction capacitance. The diode may be omitted if the efficiency loss can be tolerated. Calculating IC Operating Current This section shows how to use the values supplied in the Electrical Characteristics table to estimate operating current for a given application. The total IC operating current through DCIN when AC is present and batteries are charging (IDCIN_CHG) is given by: IDCIN_CHG = ICH1 + IVCC2_AC1 + ISAFETY1 + ISAFETY2 + IVLIM + IILIM + ISMB + ISMB_BAT1 + ISMB_BAT2 + ISMBALERT where: ICH1 is defined in "Electrical Characteristics." IVCC2_AC1 is defined in "Electrical Characteristics." ISAFETYX is the current used to test the battery thermistor connected to SAFETY1 OR SAFETY2. For thermistors that are OVER-RANGE: ISAFETYX = 2/64 * VVCC2/(RXB + RTHX) For thermistors that are COLD-RANGE: ISAFETYX = 4/64 * VVCC2/(RXB + RTHX)
1760f
W
UU
35
LTC1760
APPLICATIO S I FOR ATIO
For thermistors that are IDEAL-RANGE: ISAFETYX = 4/64 * VVCC2/(RXB + RTHX) + 2/64 * VVCC2/ (R1A +RTHX) For thermistors that are HOT-RANGE: ISAFETYX = 4/64 * VVCC2/(RXB + RTHX) + 4/64 * VVCC2/ (R1A +RTHX) RTHX is the impedance of the battery's thermistor to ground. RXB = 54.9k RXA = 1.13k Sample calculation of ISAFETYX with VVCC2 = 5.2V
Thermistor Impedance RTHX () 100k 3.3k 400 Thermistor Range OVER_RANGE IDEAL_RANGE UNDER_RANGE ISAFETYX (A) 1.05 42.2 218
IVLIM = VVCC2/(RVLIMIT + RLIM_PU). IILIM = VVCC2/(RILIMIT + RLIM_PU). RLIM_PU is the typical pull-up impedance at VLIMIT and ILIMIT. RLIM_PU = 34k. RVLIMIT is the value of the resistance from VLIMIT to GND. RILIMIT is the value of the resistance from ILIMIT to GND. ISMB is the current used for communicating with the SMBus Host and depends on the amount of bus traffic. ISMB_BATX is the current used for communicating with Battery1 or Battery2. ISMB_BATX = 350A * 0.0155 = 5.425A. ISMBALERT is defined in "Electrical Characteristics." Sample calculation of IDCIN_CHG with two Li-Ion batteries (RTHX = 400), RVLIMIT = RILIMIT = 30k, VCC2 = 5.2V, and no SMBus Host communication:
36
U
IDCIN_CHG = ICH1 + IVCC2_AC1 + ISAFETY1 + ISAFETY2 + IVLIM + IILIM + ISMB + ISMB_BAT1 + ISMB_BAT2 + ISMBALERT = 1.3mA + 700A + 218A + 218A +81A + 81A + 0A + 5.4A + 5.4A + 0A = 2.62mA The total operating current through BAT1 and BAT2 when AC is not present (IBAT_NOAC) is given by: IBAT_NOAC = IBAT + IVCC2_AC0 + ISAFETY1 + ISAFETY2 + ISMB + ISMB_BAT1_AC0 + ISMB_BAT2_AC0 + ISMBALERT where: IBAT is defined in "Electrical Characteristics." IVCC2_AC0 is defined in "Electrical Characteristics." ISAFETYX is the current used to test the battery thermistor connected to SAFETY1 or SAFETY2. ISAFETYX = 2/64 * VVCC2/(RXB + RTHX). RTHX is the impedance of the battery's thermistor to ground. RXB = 54.9k. Sample calculation of ISAFETY with VVCC2 = 5.2V
Thermistor Impedance RTHX () 400 Thermistor Range UNDER_RANGE ISAFETYX (A) 2.9
W
UU
ISMB_BATX_ACO is the current used for communicating with Battery1 or Battery2 when AC in not present. ISMB_BATX_AC0 = 350A * 0.00687 = 2.404A. ISMB is the current used for communicating with the SMBus Host and depends on the amount of bus traffic. Sample calculation with two Li-Ion batteries (RTHX = 400), VCC2 = 5.2V, and no SMBus Host communication: IBAT_NOAC - IBAT + IVCC2_AC0 + ISAFETY1 + ISAFETY2 + ISMB + ISMB_BAT1_AC0 + ISMB_BAT2_AC0 + ISMBALERT = 175A + 80A + 2.9A + 2.9A + 0A + 2.4A + 2.4A + 0A = 265A
1760f
LTC1760
APPLICATIO S I FOR ATIO
Calculating IC Power Dissipation
The power dissipation of the LTC1760 is dependent upon the gate charge of QTG and QBG.(Refer to Typical Application). The gate charge is determined from the manufacturer's data sheet and is dependent upon both the gate voltage swing and the drain voltage swing of the FET. PD = (VDCIN - VVCC) * fOSC * (QTG + QBG) + VDCIN * IDCIN_CHG - VVCC * (ISAFETY1 + ISAFETY2) where: IDCIN_CHG, ISAFETY1, ISAFETY2 are defined in the previous section. Example: VVCC = 5.2V, VDCIN = 19V, fOSC = 345kHz, QTG = QBG = 15nC, IDCIN_CHG = 2.62mA, ISAFETY1 = ISAFETY2 = 218A. PD = 190mW VSET/ISET Capacitors Capacitor C7 is used to filter the delta-sigma modulation frequency components to a level which is essentially DC. Acceptable voltage ripple at ISET is about 10mVP-P. Since the period of the delta-sigma switch closure, T, is about 10s and the internal IDAC resistor, RSET, is 18.77k, the ripple voltage can be approximated by:
VISET =
VREF * T RSET * C 7
Then the equation to extract C7 is:
VREF * T VISET * RSET = 0.8/0.01/18.77k(10s) 0.043F In order to prevent overshoot during start-up transients the time constant associated with C7 must be shorter than the time constant of C5 at the ITH pin. If C7 is increased to improve ripple rejection, then C5 should be increased proportionally and charger response time to average current variation will degrade. C7 =
Capacitors CB1 and CB2 are used to filter the VDAC deltasigma modulation frequency components to a level which
U
is essentially DC. CB2 is the primary filter capacitor and CB1 is used to provide a zero in the response to cancel the pole associated with CB2. Acceptable voltage ripple at VSET is about 10mVP-P. Since the period of the delta-sigma switch closure, T, is about 11s and the internal VDAC resistor, RVSET, is 7.2k, the ripple voltage can be approximated by:
W
UU
VVSET =
VREF * T RVSET C B1 || C B2
(
)
Then the equation to extract CB1 || CB2 is:
C B1 || C B2 =
VREF * T RVSET VVSET
CB2 should be 10x to 20x CB1 to divide the ripple voltage present at the charger output. Therefore CB1 = 0.01F and CB2 = 0.1F are good starting values. In order to prevent overshoot during start-up transients the time constant associated with CB2 must be shorter than the time constant of C5 at the ITH pin. If CB2 is increased to improve ripple rejection, then C5 should be increased proportionally and charger response time to voltage variation will degrade. Input and Output Capacitors In the 4A Lithium Battery Charger (Typical Application section), the input capacitor (CIN) is assumed to absorb all input switching ripple current in the converter, so it must have adequate ripple current rating. Worst-case RMS ripple current will be equal to one half of output charging current. Actual capacitance value is not critical. Solid tantalum low ESR capacitors have high ripple current rating in a relatively small surface mount package, but caution must be used when tantalum capacitors are used for input or output bypass. High input surge currents can be created when the adapter is hot-plugged to the charger or when a battery is connected to the charger. Solid tantalum capacitors have a known failure mechanism when subjected to very high turn-on surge currents. Only Kemet T495 series of "Surge Robust" low ESR tantalums are rated for high surge conditions such as battery to ground.
1760f
37
LTC1760
APPLICATIO S I FOR ATIO
The relatively high ESR of an aluminum electrolytic for C15, located at the AC adapter input terminal, is helpful in reducing ringing during the hot-plug event. Refer to AN88 for more information. Highest possible voltage rating on the capacitor will minimize problems. Consult with the manufacturer before use. Alternatives include new high capacity ceramic (at least 20F) from Tokin, United Chemi-Con/Marcon, et al. Other alternative capacitors include OSCON capacitors from Sanyo. The output capacitor (COUT) is also assumed to absorb output switching current ripple. The general formula for capacitor current is:
0.29 (VBAT) 1 - IRMS =
For example:
(
VBAT VDCIN
)
(L1)(f)
VDCIN = 19V, VBAT = 12.6V, L1 = 10H, and f = 300kHz, IRMS = 0.41A. EMI considerations usually make it desirable to minimize ripple current in the battery leads, and beads or inductors may be added to increase battery impedance at the 300kHz switching frequency. Switching ripple current splits between the battery and the output capacitor depending on the ESR of the output capacitor and the battery impedance. If the ESR of COUT is 0.2 and the battery impedance is raised to 4 with a bead or inductor, only 5% of the current ripple will flow in the battery. Power Path and Charge MUX MOSFET Selection Three pairs of P-channel MOSFETs must be used with the wall adapter and the two battery discharge paths. Two pairs of N-channel MOSFETs must be used with the battery charge path. The nominal gate drive levels are set by the clamp drive voltage of their respective control circuitry. This voltage is typically 6.25V. Consequently, logic-level threshold MOSFETs must be used. Pay close attention to the BVDSS specification for the MOSFETs as well; many of the logic level MOSFETs are limited to 30V or less.
38
U
Selection criteria for the power MOSFETs include the "ON" resistance RDS(ON), input voltage and maximum output current. For the N-channel charge path, the maximum current is the maximum programmed current to be used. For the P-channel discharge path maximum current typically occurs at end of life of the battery when using only one battery. The upper limit of RDS(ON) value is a function of the actual power dissipation capability of a given MOSFET package that must take into account the PCB layout. As a starting point, without knowing what the PCB dissipation capability would be, derate the package power rating by a factor of two. RDS(ON)MAX = PMOSFET 2 IMAX
W
UU
()
2
If you are using a dual MOSFET package with both MOSFETs in series, you must cut the package power rating in half again and recalculate. RDS(ON)MAX = PMOSFETDUAL 4 IMAX
()
2
If you use identical MOSFETs for both battery paths, voltage drops will track over a wide current range. The LTC1760 linear 25mV CV drop regulation will not occur until the current has dropped below:
ILINEARMAX =
25mV 2 RDS(ON)MAX
However, if you try to use the above equation to determine RDS(ON) to force linear mode at full current, the MOSFET RDS(ON) value becomes unreasonably low for MOSFETs available at this time. The need for the LTC1760 voltage drop regulation only comes into play for parallel battery configurations that terminate charge or discharge using voltage. At first this seems to be a problem, but there are several factors helping out: 1. When batteries are in parallel current sharing, the current flow through any one battery is less than if it is running stand-alone. 2. Most batteries that charge in constant voltage mode, such as Li-ion, charge terminate at a current value of
1760f
LTC1760
APPLICATIO S I FOR ATIO
C/10 or less which is well within the linear operation range of the MOSFETs. 3. Voltage tracking for the discharge process does not need such precise voltage tracking values. The LTC1760 has two transient conditions that force the discharge path P-channel MOSFETs to have two additional parameters to consider. The parameters are gate charge QGATE and single pulse power capability. When the LTC1760 senses a LOW_POWER event, all the P-channel MOSFETs are turned on simultaneously to allow voltage recovery due to a loss of a given power source. However, there is a delay in the time it takes to turn on all the MOSFETs. Slow MOSFETs will require more bulk capacitance to hold up all the system's power supply function during the transition and fast MOSFET will require less bulk capacitance. The transition speed of a MOSFET to an on or off state is a direct function of the MOSFET gate charge. t = QGATE/IDRIVE IDRIVE is the fixed drive current into the gate from the LTC1760 and "t" is the time it takes to move that charge to a new state and change the MOSFET conduction mode. Hence time is directly related to QGATE. Since QGATE goes up with MOSFETs of lower RDS(ON), choosing such MOSFETs has a counterproductive increase in gate charge making the MOSFET slower. Please note that the LTC1760 recovery time specification only refers to the time it takes for the voltage to recover to the level just prior to the LOW_POWER event as opposed to full voltage. The single pulse current rating of MOSFET is important when a short-circuit takes place. The MOSFET must survive a 15ms overload. MOSFETs of lower RDS(ON) or MOSFETs that use more powerful thermal packages will have a high power surge rating. Using too small of a pulse rating will allow the MOSFET to blow to the open circuit condition instantly like a fuse. Typically there is no outward sign of failure because it happens so fast. Please measure the surge current for all discharge power paths under worse case conditions and consult the MOSFET data sheet for the limitations. Voltage sources with the highest voltage and the most bulk capacitance are often the biggest risk. Specifically the MOSFETs in the wall
U
adapter path with wall adapters of high voltage, large bulk capacitance and low resistance DC cables between the adapter and device are the most common failures. Remember to only use the real wall adapter with a production DC power cord when performing the wall adapter path test. The use of a laboratory power supply is unrealistic for this test and will force you to over specify the MOSFET ratings. A battery pack usually has enough series resistance to limit the peak current or are too low in voltage to create enough instantaneous power to damage their respective power path MOSFETs. Conditioning Systems With Large Loads In systems where the load is too large to be used for conditioning a single battery it may be necessary to bypass the built in calibrate function and simply switch in an external load. A convenient way to accomplish this task is by using an SMBus based LTC1623 load switch controller. See Figure 10.
PowerPath MUX LTC1760 CHARGE MUX SMBus TO LOAD SMBus TO/FROM HOST LTC1623 CONDITIONING LOAD
1760 F10
W
UU
Figure 10
Unique Configuration Information This section summarizes unique LTC1760 configurations that allow some LTC1760 features to be eliminated. These configurations may be selected in any combination without adversely affecting LTC1760 operation. Refer to the Typical Application circuit diagram located at the back of this data sheet.
1760f
39
LTC1760
APPLICATIO S I FOR ATIO
A) Single Battery Configuration. To limit the LTC1760 to a single battery, modify the battery slot to be eliminated as follows: 1) Remove both FETs (Q5, Q6 or Q7, Q8) involved in the charge path. 2) Remove both FETS (Q3, Q4 or Q9, Q10) involved in the discharge path. 3) Remove the thermistor sensing resistors (R1A, R1B or R2A, R2B). 4) Short the thermistor sense lines together at the IC. 5) Remove the diode (D2 or D3) as required. 6) Unless otherwise specified, leave the unused pins of the LTC1760 floating. B) No Short-Circuit Protection Configuration. 1) Replace RSC with a short. C) No LOPWR Protection. 1) Remove resistors R2 and R3 connected to LOPWR and tie LOPWR to the VCC pin. D) No DC Path Configuration. To remove the DC input as part of the power path choices to support the load: 1) Remove both FETs Q1 and Q2 involved in the DC path. 2) Unless otherwise specified, leave the unused pins of the LTC1760 floating. E) No Charge Configuration. To permanently disable the battery charger function: 1) Remove ALL FETs involved in the charge path (Q3, Q4, Q9, Q10). 2) Remove switching FETs QTG, QBG, diode D1 and inductor L1. 3) Remove diodes D2, D3, D4, capacitors C4, COUT and Resistor R11 and RSENSE. 4) Reduce CIN capacitor to 0.1F. PCB Layout Considerations For maximum efficiency, the switch node rise and fall times should be minimized. To prevent magnetic and electrical field radiation and high frequency resonant problems, proper layout of the components connected to the IC is essential. (See Figure 11.) Here is a PCB layout priority list for proper layout. Layout the PCB using this specific order. 1. Input capacitors need to be placed as close as possible to switching FET's supply and ground connections. Shortest copper trace connections possible. These parts must be on the same layer of copper. Vias must not be used to make this connection. 2. The control IC needs to be close to the switching FET's gate terminals. Keep the gate drive signals short for a clean FET drive. This includes IC supply pins that connect to the switching FET source pins. The IC can be placed on the opposite side of the PCB relative to above. 3. Place inductor input as close as possible to switching FET's output connection. Minimize the surface area of this trace. Make the trace width the minimum amount needed to support current--no copper fills or pours. Avoid running the connection using multiple layers in parallel. Minimize capacitance from this node to any other trace or plane.
40
U
5) Remove all components connected to COMP1, VSET, ITH, ISET, ILIMIT and VLIMIT pins. 6) Short ILIMIT and VLIMIT to VSS. 6) Remove R1, C1 but short CLP to DCIN. Replace RCL with a short/trace connection. 7) Short CSP to CSN but leave the combination floating. 8) Unless otherwise specified, leave the unused pins of the LTC1760 floating. F) No DC Path And No Charge Configuration. To limit the LTC1760 to battery discharge functions only, merge the previous two configurations with the following: 1) Remove CIN. 2) Remove resistors tied to DCDIV and ground DCDIV.
1760f
W
UU
LTC1760
APPLICATIO S I FOR ATIO
SWITCH NODE L1 VBAT HIGH FREQUENCY CIRCULATING PATH
VIN
CIN
D1
COUT
Figure 11. High-Speed Switching Path
4. Place the output current sense resistor right next to the inductor output but oriented such that the IC's current sense feedback traces going to resistor are not long. The feedback traces need to be routed together as a single pair on the same layer at any given time with smallest trace spacing possible. Locate any filter component on these traces next to the IC and not at the sense resistor location. 5. Place output capacitors next to the sense resistor output and ground. 6. Output capacitor ground connections need to feed into same copper that connects to the input capacitor ground before tying back into system ground. General Rules 7. Connection of switching ground to system ground or internal ground plane should be single point. If the system has an internal system ground plane, a good way to do this is to cluster vias into a single star point to make the connection. 8. Route analog ground as a trace tied back to IC ground (analog ground pin if present) before connecting to any other ground. Avoid using the system ground plane. CAD trick: make analog ground a separate ground net and use a 0 resistor to tie analog ground to system ground.
U
9. A good rule of thumb for via count for a given high current path is to use 0.5A per via. Be consistent. 10. If possible, place all the parts listed above on the same PCB layer. 11. Copper fills or pours are good for all power connections except as noted above in Rule 3. You can also use copper planes on multiple layers in parallel too--this helps with thermal management and lower trace inductance improving EMI performance further. 12. For best current programming accuracy provide a Kelvin connection from RSENSE to CSP and BAT. See Figure 12 as an example. It is important to keep the parasitic capacitance on the RT, CSP and BAT pins to a minimum. The traces connecting these pins to their respective resistors should be as short as possible.
DIRECTION OF CHARGING CURRENT
W
UU
BAT
1760 F10
RSNS
1760 F11
CSP
CSN
Figure 12. Kelvin Sensing of Charging Current
Important Safety Notes Although every effort is made to meet and exceed all required "SMBus Charger V1.1" safety features it is the responsibility of the battery pack to protect itself from excessive currents or voltages. The LTC1760 is not itself a safety device. Consult your battery pack manufacturer for more information.
1760f
41
LTC1760
TYPICAL APPLICATIO U
Application for a Dual Battery System (12.6V/4A)
PowerPath MUX VIN C8, 1F C1 0.1F LTC1760 R10, 100 C9, 0.1F Q1 Q6 Q7 36 CLP 41 DCIN 3 BAT1 2 BAT2 VPLUS GDCI GDCO GB1I GB1O GB2I GB2O SCP 16 SCN DCDIV 37 LOPWR COMP1 47 CSN GCH2 48 CSP SCH2 46 ITH GCH1 45 ISET SCH1 13 SW V 40 SET BOOST V 24 CC TGATE VSS BGATE PGND 25 TH2A V 29 CC2 TH2B SMBALERT 18 SCL2 SCL 22 SDA2 SDA 20 TH1A V 33 DDS TH1B V 32 LIMIT SCL1 I 26 LIMIT SDA1 MODE BAT2 D2 I6 R11 1k C13 0.1F CB1, 0.1F BAT1 D3 I5 D4 C4, 0.22F CB2 0.47F C6 4.7F R6 100 QBG D1 1 7 6 9 8 11 10 5 4 12 34 35 14 15 42 43 44 39 38 28 27 17 21 30 31 19 23 Q2 Q5 Q8 RSC 0.02 LOAD R2 280k R3 49.9k CL 20F C7 0.1F R9 3.3k C12 1000pF C5 0.15F R2A, 1.13k SAFETY 2 R2B, 54.9k TH SCL SDA BAT1 BAT2 R1A, 1.13k SAFETY 1 R1B, 54.9k TH SCL SDA QTG L1 10H RSENSE 0.025 CIN 20F COUT 20F CHARGE MUX Q4 Si6928 Q3 Si6928 Q9 Si6928 Q10 Si6928
1760 TA02
RCL 0.03 R1 4.99k
R4 12.7k
R5 1.21k
R7 49.9k C3 0.012F
C11 1800pF
VDDS SMBALERT SCL SDA VDDS RVLIMIT 10k RPU RPU
C1 0.1F
D1: MBR130T3 D2: IN4148 TYPE Q1, Q2, Q5, Q6, Q7, Q8: Si4925DY Q3, Q4, Q9, Q10, QTG, QBG: FDS6912A
1760f
42
LTC1760
PACKAGE DESCRIPTIO
48
25 0.95 0.10
8.1 0.10
6.2 0.10 7.9 - 8.3 (.311 - .327)
1 0.32 0.05
24 0.50 BSC 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 1.10 (.0433) MAX
RECOMMENDED SOLDER PAD LAYOUT 6.0 - 6.2** (.236 - .244)
0.25 REF 0 - 8
0.09 - 0.20 (.0035 - .008)
0.45 - 0.75 (.018 - .029)
NOTE: 1. CONTROLLING DIMENSION: MILLIMETERS MILLIMETERS 2. DIMENSIONS ARE IN (INCHES) 3. DRAWING NOT TO SCALE *DIMENSIONS DO NOT INCLUDE MOLD FLASH. MOLD FLASH SHALL NOT EXCEED .152mm (.006") PER SIDE **DIMENSIONS DO NOT INCLUDE INTERLEAD FLASH. INTERLEAD FLASH SHALL NOT EXCEED .254mm (.010") PER SIDE
Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights.
U
FW Package 48-Lead Plastic TSSOP (6.1mm)
(Reference LTC DWG # 05-08-1651)
12.40 - 12.60* (.488 - .496) 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 -C0.50 (.0197) BSC 0.17 - 0.27 (.0067 - .0106) TYP 0.05 - 0.15 (.002 - .006) -T0.10 C
FW48 TSSOP 0204
1760f
43
LTC1760
RELATED PARTS
PART NUMBER LT1571 LTC1733 LT1769 LTC1960 LTC4006 DESCRIPTION 1.5A Switching Regulator Battery Charger Li-Ion Linear Charger with Thermal Regulation 2A Switching Regulator Battery Charger Dual Battery Charger/Selector with SPI Small, High Efficiency, Fixed Voltage, Lithium-Ion Battery Charger High Efficiency, Programmable Voltage Battery Charger with Termination High Efficiency, Programmable Voltage/ Current Battery Charger Smart Battery Charger Controller COMMENTS 500kHz or 200kHz Switching Frequency for Small Design Will Not Overheat, Standalone Charger, Complete Charger Monolithic, 20-Lead TSSOP, 28-Lead SSOP Packages 11-Bit VDAC, 0.8% Voltage Accuracy, 10-Bit IDAC for 5% Current Accuracy Constant Current/ Constant Voltage Switching Regulator with Termination Timer; AC Adapter Current Limit and SafetySignal Sensor in a Small 16 Pin Package Complete Charger for 3- or 4-Cell Lithium-Ion Batteries, AC Adapter Current Limit, SafetySignal Sensor and Indicator Outputs Constant Current/ Constant Voltage Switching Regulator; Resistor Voltage/Current Programming, AC Adapter Current Limit and SafetySignal Sensor SMBus Rev 1.1 Compliant
LTC4007 LTC4008
LTC4100
1760f
44
Linear Technology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7417
(408) 432-1900
LT/TP 1004 1K * PRINTED IN USA
FAX: (408) 434-0507 www.linear.com
(c) LINEAR TECHNOLOGY CORPORATION 2003

▲Up To Search▲

Price & Availability of LTC17601

	To Download LTC17601 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .